參數(shù)資料
型號： EVAL-ADUC7036QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 92/132頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADUC7036
設(shè)計資源： EVAL-ADUC7036 Schematic & Brd Outline
EVAL ADUC7036 Gerber Files
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ PLUS 套件
主要目的： 電源管理，電池監(jiān)控器
嵌入式： 是，MCU，16/32 位
已用 IC / 零件： ADuC7036
已供物品： 板，線纜，文檔，仿真器，電源，軟件
ADuC7036
Rev. C | Page 62 of 132
SYSTEM CLOCKS
The ADuC7036 integrates a very flexible clocking system that
allows clock generation from one of three sources: an integrated
on-chip precision oscillator, an integrated on-chip low power
oscillator, or an external watch crystal. These three options are
shown in Figure 30.
Each of the internal oscillators is divided by 4 to generate a clock
frequency of 32.768 kHz. The PLL locks onto a multiple (625)
of 32.768 kHz, supplied by either of the internal oscillators or
the external crystal to provide a stable 20.48 MHz clock for the
system. The core can operate at this frequency or at a binary
submultiple of this frequency, thereby allowing power saving
when peak performance is not required.
By default, the PLL is driven by the low power oscillator that
generates a 20.48 MHz clock source. The ARM7TDMI core, in
turn, is driven by a clock divider (set by the CD bits in the
POWCON register). By default, the CD bits are configured to
divide the PLL output by 2, thereby generating a core clock of
10.24 MHz. The divide factor can be modified to generate a
binary-weighted divider factor in the range of 1 to 128 that can
be altered dynamically by user code.
The ADC is driven by the output of the PLL, which is divided to
provide an ADC clock source of 512 kHz. In low power mode,
the ADC clock source is switched from the standard 512 kHz to
the low power 131 kHz oscillator.
Note that the low power oscillator drives both the watchdog and
core wake-up timers through a divide-by-4 circuit. A detailed
block diagram of the ADuC7036 clocking system is shown in
SPI
CORE CLOCK
PLL OUTPUT
(20.48MHz)
UART
CORE CLOCK
PRECISION
131kHz
DIV 4
PRECISION
OSCILLATOR
LOW POWER
OSCILLATOR
EXTERNAL
32.768kHz
LOW POWER
131kHz
DIV 4
PLLCON
PLL
FLASH
CONTROLLER
ECLK 2.5MHz
PRECISION
32.768kHz
LOW POWER
32.768kHz
PLL OUTPUT
20.48MHz
CRYSTAL
CIRCUITRY
EXTERNAL CRYSTAL
(OPTIONAL)
PLL LOCK
1
8
ADCMDE
CLOCK
DIVIDER
CORE
CLOCK
1
2CD
MCU
ADC
CLOCK
ADC
HIGH ACCURCY
CALIBRATION
COUNTER
EXTERNAL
32.768kHz
PRECISION
131kHz
LOW POWER
CALIBRATION
COUNTER
LOW POWER
OSCILLATOR
TIMER0
LIFETIME
CORE CLOCK
EXTERNAL
32.768kHz
PRECISION
32.768kHz
LOW POWER
32.768kHz
GPIO_5
TIMER1
GENERAL-PURPOSE
CORE CLOCK
GPIO_8
LOW POWER
32.768kHz
TIMER2
WAKE-UP
CORE CLOCK
LOW POWER
32.768kHz
PRECISION
32.768kHz
EXTERNAL
32.768kHz
WATCHDOG
TIMER3
LOW POWER
32.768kHz
TIMER4
STI
LOW POWER
32.768kHz
CORE CLOCK
LIN H/W
SYNCHRONIZATION
LOW POWER
32.768kHz
PLL OUTPUT
(5MHz)
0
74
-0
29
Figure 30. System Clock Generation
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