參數(shù)資料
型號： EVAL-ADUC7036QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 7/132頁
文件大小： 0K
描述： BOARD EVAL FOR ADUC7036
設(shè)計資源： EVAL-ADUC7036 Schematic & Brd Outline
EVAL ADUC7036 Gerber Files
標準包裝： 1
系列： QuickStart™ PLUS 套件
主要目的： 電源管理，電池監(jiān)控器
嵌入式： 是，MCU，16/32 位
已用 IC / 零件： ADuC7036
已供物品： 板，線纜，文檔，仿真器，電源，軟件
ADuC7036
Rev. C | Page 104 of 132
UART SERIAL INTERFACE
The ADuC7036 features a 16,450-compatible UART. The UART
is a full-duplex, universal, asynchronous receiver/transmitter. A
UART performs serial-to-parallel conversion on data characters
received from a peripheral device and performs parallel-to-serial
conversion on data characters received from the ARM7TDMI.
The UART features a fractional divider that facilitates high accu-
racy baud rate generation and a network addressable mode. The
UART functionality is available on the GPIO_5/IRQ1/RxD and
GPIO_6/ TxD pins of the ADuC7036.
The serial communication adopts an asynchronous protocol that
supports various word lengths, stop bits, and parity generation
options selectable in the configuration register.
BAUD RATE GENERATION
The ADuC7036 features two methods of generating the UART
baud rate: normal 450 UART baud rate generation and ADuC7036
fractional divider baud rate generation.
Normal 450 UART Baud Rate Generation
The baud rate is a divided version of the core clock using the
value in COMDIV0 and COMDIV1 MMRs (each is a 16-bit
value, DL). The standard baud rate generator formula is
DL
Rate
Baud
CD
×
=
2
16
2
MHz
48
.
20
(1)
Table 79 lists common baud rate values.
Table 79. Baud Rate Using the Standard Baud Rate Generator
Baud Rate (bps)
CD
DL
Actual Baud Rate
% Error
9600
0
0x43
9552
0.50%
19,200
0
0x21
19,394
1.01%
115,200
0
0x6
106,667
7.41%
9600
3
0x8
10,000
4.17%
19,200
3
0x4
20,000
4.17%
115,200
3
0x1
80,000
30.56%
Fractional Divider
The fractional divider, combined with the normal baud rate
generator, allows the generation of accurate, high speed baud rates.
/2
/(M+N/2048)
/16DL
UART
CORE
CLOCK
FBEN
0
747
4-
0
40
Figure 43. Fractional Divider Baud Rate Generation
Calculation of the baud rate using a fractional divider is as follows:
)
2048
(
2
16
2
MHz
48
.
20
N
M
DL
Rate
Baud
CD
+
×
=
(2)
2
16
2
MHz
48
.
20
2048
×
=
+
DL
Rate
Baud
N
M
CD
where:
CD is the clock divider.
DL is the divisor latch.
M is the integer part of the divisor; a fractional divider divides
an input by a nonwhole number, M.N.
N is the fractional part of the divisor; a fractional divider
divides an input by a nonwhole number, M.N.
Table 80 lists common baud rate values.
Table 80. Baud Rate Using the Fractional Baud Rate Generator
Baud Rate
(bps)
CD
DL
M
N
Actual
Baud Rate
% Error
9600
0
0x42
1
21
9598.55
0.015%
19,200
0
0x21
1
21
19,197.09
0.015%
115,200
0
0x5
1
228
115,177.51
0.0195%
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