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參數(shù)資料
| 型號： | EM6821TQ52B |
| 英文描述： | Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: 0°C to 70°C; Package: 8-EPSOIC |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 8/69頁 |
| 文件大?。?/td> | 852K |
| 代理商： | EM6821TQ52B |
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EM6821
10/01, Revision A/386
Copyright
2001, EM Microelectronic-Marin SA
16
www.emmicroelectronic.com
Table 6.3.2 Register RegIRQMask1
Bit
Name
Reset
R/W
Description
3
MaskIRQPA[3]
0
R/W
Interrupt mask for PA[3] input
2
MaskIRQPA[2]
0
R/W
Interrupt mask for PA[2] input
1
MaskIRQPA[1]
0
R/W
Interrupt mask for PA[1] input
0
MaskIRQPA[0]
0
R/W
Interrupt mask for PA[0] input
Default "0" is: interrupt request masked, no new request stored
Table 6.3.3 Register RegIRQ1
Bit
Name
Reset
R/W
Description
3
IRQPA[3]
0
R/W*
Interrupt request on PA[3]
2
IRQPA[2]
0
R/W*
Interrupt request on PA[2]
1
IRQPA[1]
0
R/W*
Interrupt request on PA[1]
0
IRQPA[0]
0
R/W*
Interrupt request on PA[0]
*; Write "1" clears the bit, write "0" has no action, default "0" is: no interrupt request
Table 6.3.4 Register OPTIntEdgPA
Bit
Name
power on
value
R/W
Description
3
IntEdgPA[3]
0
R/W
Interrupt edge select for PA[3]
2
IntEdgPA[2]
0
R/W
Interrupt edge select for PA[2]
1
IntEdgPA[1]
0
R/W
Interrupt edge select for PA[1]
0
IntEdgPA[0]
0
R/W
Interrupt edge select for PA[0]
Default "0" is: Positive edge selection
Table 6.3.5 Register OPTDebIntPA
Bit
Name
power on
value
R/W
Description
3
NoDebIntPA[3]
0
R/W
Interrupt debounced for PA[3]
2
NoDebIntPA[2]
0
R/W
Interrupt debounced for PA[2]
1
NoDebIntPA[1]
0
R/W
Interrupt debounced for PA[1]
0
NoDebIntPA[0]
0
R/W
Interrupt debounced for PA[0]
Default "0" is: Debounced inputs for interrupt generation
Table 6.3.6 Register OPTNoPullPA
Bit
Name
power on
value
R/W
Description
3
NoPullPA[3]
0
R/W
Pull-up/down selection on PA[3]
2
NoPullPA[2]
0
R/W
Pull-up/down selection on PA[2]
1
NoPullPA[1]
0
R/W
Pull-up/down selection on PA[1]
0
NoPullPA[0]
0
R/W
Pull-up/down selection on PA[0]
Default "0" depending on mask selection
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