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| 型號： | EM6821TQ52B |
| 英文描述： | Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: 0°C to 70°C; Package: 8-EPSOIC |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 42/69頁 |
| 文件大?。?/td> | 852K |
| 代理商： | EM6821TQ52B |
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EM6821
10/01, Revision A/386
Copyright
2001, EM Microelectronic-Marin SA
47
www.emmicroelectronic.com
14.1 LCD Control
The LCD driver has two control registers RegLCDCntl1, RegLCDCntl2 to optimize for display contrast, power
consumption, operation mode and bias voltage source.
LCDExtSupply:
Choosing external supply (LCDExtSupply =‘1’) disables the internal LCD voltage regulator
and voltage multiplier, it also puts the bias voltage terminals VL1, VL2 and VL3 into high impedance state.
External bias levels can now be connected to VL1, VL2 and VL3 terminals. (Resistor divider chain or others).
Another way to adapt the VL1, VL2 and VL3 levels to specific user needs is to overdrive the VL1 output
(LCDExtSupply
=0) with the desired value. The internal multiplier will multiply this new VL1 level to generate
the corresponding levels VL2 and VL3. The bit LCDExtSupply is only reset by initial POR.
LCD4Mux:
With this switch one selects either 3:1 or 4:1 (default) times multiplexing of the 20 Segment driver
outputs. In the case of 3:1 multiplexing the COM[4] is off.
LCDOff:
Disables the LCD. The voltage multiplier and regulator are switched off ( 0 current ).The Segment
latch information is maintained. The VL1,VL2 and VL3 outputs are pulled to VSS.
LCDBlank:
All Segment outputs are turned off. The voltage multiplier and regulator remain switched on.
LCDBlank
can be used with the 1Hz and Blink interrupt to let the whole display blink (software controlled).
CkTripSel1,0:
Selecting the appropriate voltage multiplier frequency to optimize display contrast and power
consumption. The value to use is also depending on the selected multiplier booster capacitors (typically 100nF).
14.2 LCD Addressing
The LCD driver addressing is indirect using
the RegIndexAdr value as an offset to the
directly addressed base LCD_1, LCD_2 or
LCD_3
registers. All LCD Segment registers
are R/W.
At address LCD_3 only the first 8 Index
locations are usable. The Index locations
hex(8 to F) are non implemented.
A total of 40 addresses are available to the
user to freely define the addressing of the
LCD Segment latches. For each of these
latches the user may choose the address
and data to be connected. See also section
14.3. However only 20x4 LCD Segment
latches are implemented. The unused
address locations are empty and can not be
used as RAM.
Figure 36. LCD Address Mapping
LCD_3
LCD_2
LCD_1
4 bit R/W
RegIndexAdr[F]
RegIndexAdr[E]
4 bit R/W
...
RegIndexAdr[1]
4 bit R/W
RegIndexAdr[0]
4 bit R/W
RegIndexAdr[F]
RegIndexAdr[E]
4 bit R/W
...
RegIndexAdr[1]
4 bit R/W
RegIndexAdr[0]
4 bit R/W
RegIndexAdr[8]
RegIndexAdr[7]
4 bit R/W
...
RegIndexAdr[1]
4 bit R/W
RegIndexAdr[0]
40 x 4 Indexed Addressable LCD Latches
but Maximum 20x4 Bits are R/W
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