參數(shù)資料
型號(hào)： EM6821TQ52B
英文描述： Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: 0&degC to 70°C; Package: 8-EPSOIC
中文描述： 微控制器
文件頁(yè)數(shù)： 17/69頁(yè)
文件大?。?/td> 852K
代理商： EM6821TQ52B
EM6821
10/01, Revision A/386
Copyright
2001, EM Microelectronic-Marin SA
24
www.emmicroelectronic.com
6.6.7 Reset and Sleep on Port SP
During circuit initialization, all option registers are reset by Power On Reset and therefore all pull-ups are off and
all pull-downs are on. During Sleep mode, Port SP inputs are cut-off , the circuit is in Reset State. However the
Reset State does not reset the option registers and pull-downs, if previously turned on, remain on even during
Sleep mode. After any reset the serial interface parameters are reset to : Slave mode, Start and Status = 0, LSB
first, negative edge shift , PSP[3:0] tristate.
Note :
A write operation in the control registers or in the data registers while Start is high will change internal
values and may cause an error condition. The user must take care of the serial interface status before writing
internal registers. In order to read the correct values on the data registers, the shift operation must be halted
during the read accesses.
Figure 17 Shift Operation and IRQ Generation
SCLK = System Clock;
Active Edge = Neg. Edge;
Sense = MSB First
Clock Source
Shift Ck
Start
IRQ
Shift
Register
SIN
OM[1]=1, OM[0]=0 : direct data out on pos. or neg. SCLK clock edge depending on bit POSnNeg
SOUT
OM[1]=0, OM[0]=1 : Re-Synchronized on positive SCLK clock edge data out
SOUT
10010011
01001100
01
1
0
1
0
1
10
0
1
0
01
1
0
1
0
1
Figure 18. Sample Basic Serial Port Connections
optional connection
External
EM6621
SP[2]; SOUT
SP[3]; SCLKIn
SP[0]; SIN
SP[1]; Status
Serial Data In
Serial Clock Out
Serial Data Out
Ready
External
EM6621
SP[2]; SOUT
SP[3]; SCLKOut
SP[0]; SIN
Ready
SP[1]: Status
Serial Data In
Serial Clock In
Serial Data Out
Status Output
CS
Slave Mode
Master Mode
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