參數(shù)資料
型號(hào)： EM6821TQ52B
英文描述： Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: 0&degC to 70°C; Package: 8-EPSOIC
中文描述： 微控制器
文件頁(yè)數(shù)： 15/69頁(yè)
文件大?。?/td> 852K
代理商： EM6821TQ52B
EM6821
10/01, Revision A/386
Copyright
2001, EM Microelectronic-Marin SA
22
www.emmicroelectronic.com
For POWER SAVING one can switch off the port SP pull resistors between two read phases. No cross current
flows in the input amplifier while the port SP is not read.
This power saving feature must only be used in tristate mode (OM[0,1]=0). The recommended order is :
switch on the pull resistor.
allow sufficient time - RC constant - for the pull resistor to drive the line to either VSS or VDD.
Read the port SP
Switch off the pull resistor
Minimum time with current on the pull resistor is 4 periods of the system clock, if the RC constant is lower than
1 system clock period. Adding a NOP before reading moves the number of periods with current in the pull
resistor to 6 and the maximum RC delay to 3 clock periods.
6.6.3 Nch. Open Drain Outputs
The port SP outputs can be configured as either CMOS or Nch. open drain outputs.
In CMOS both logic ‘1’ and ‘0’ are driven out on the terminal.
In Nch. open drain only the logic ‘0’ is driven out on the terminal, the logic ‘1’ value is high impedance or defined
by the internal pull-up resistor (if existing).
6.6.4 General Functional Description
After power on or after any reset the serial interface is in serial slave mode with Start and Status set to 0, LSB
first, negative shift edge and all outputs are in high impedance state.
When the Start bit is set, the shift operation is enabled and the serial interface is ready to transmit or receive
data, eight shift operations are performed: 8 serial data values are read from the data input terminal into the
shift register and the previous loaded 8-bits are send out via the data output terminal. After the eight shift
operation, an interrupt is generated, and the Start bit is reset.
Parallel to serial conversion procedure ( master mode example ).
Write to RegSCntl1 serial control (clock freq. in master mode, edge and MSB/LSB select).
Write to RegSDataL and RegSDataH (shift out data values).
Write to RegSCntl2 (Start=1, mode select, status).
---> Starts the shift out
After the eighth clock an interrupt is generated, Start becomes low. Then, interrupt handling
Serial to parallel conversion procedure (slave mode example).
Write to RegSCntl1 (slave mode, edge and MSB/LSB select).
Write to RegSCntl2 (Start=1, mode select, status).
After eight serial clocks an interrupt is generated, Start becomes low.
Interrupt handling.
Shift register RegSDataL and RegSDataH read.
A new shift operation can be authorized.
Figure 15. CMOS or Nch. Open Drain outputs
I / O
Term inal
SP[n]
MUX
Active Pull-up
for High State
DR[n]
Serial Interface
Output
Tristate Output
Buffer : High
Im pedance for
Data = 1
Data
I / O
Term inal
SP[n]
MUX
DR[n]
Serial Interface
Output
Tristate Output
Buffer : closed
Data
1
CMOS Output
Nch. Open Drain Output
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