參數(shù)資料
型號： EM6821TQ52B
英文描述： Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: 0&degC to 70°C; Package: 8-EPSOIC
中文描述： 微控制器
文件頁數(shù)： 37/69頁
文件大小： 852K
代理商： EM6821TQ52B
EM6821
10/01, Revision A/386
Copyright
2001, EM Microelectronic-Marin SA
42
www.emmicroelectronic.com
Any interrupt request sent by a periphery cell while the corresponding mask is not set will not be stored in the
interrupt request register. All interrupt requests are stored in their IRQxx registers depending only on their mask
setting and not on the general interrupt enable status.
Whenever the EM6821 goes into halt mode the IntEn bit is automatically set to 1, thus allowing to resume from
halt mode with an interrupt.
10.1 Interrupt Control Registers
Table 10.1.6 Register RegIRQ1
Bit
Name
Reset
R/W
Description
3
IRQPA[3]
0
R *
Port A PA[3] interrupt request
2
IRQPA[2]
0
R *
Port A PA[2] interrupt request
1
IRQPA[1]
0
R *
Port A PA[1] interrupt request
0
IRQPA[0]
0
R *
Port A PA[0] interrupt request
*; Writing of 1 clears the corresponding bit.
Table 10.1.7 Register RegIRQ2
Bit
Name
Reset
R/W
Description
3
IRQHz1
0
R *
Prescaler interrupt request
2
IRQHz32/8
0
R *
Prescaler interrupt request
1
IRQBlink
0
R *
Prescaler interrupt request
0
IRQBz
0
R *
Melody timer interrupt request
*; Writing of 1 clears the corresponding bit.
Table 10.1.8 Register RegIRQ3
Bit
Name
Reset
R/W
Description
3
IRQSerial
0
R *
Serial interrupt request
2
IRQMSC
0
R *
Millisecond counter int. request
1
IRQCount0
0
R *
Counter interrupt request
0
IRQCntComp
0
R *
Counter interrupt request
*; Writing of 1 clears the corresponding bit.
Table 10.1.9 Register RegIRQMask1
Bit
Name
Reset
R/W
Description
3
MaskIRQPA[3]
0
R/W
Port A PA[3] interrupt mask
2
MaskIRQPA[2]
0
R/W
Port A PA[2] interrupt mask
1
MaskIRQPA[1]
0
R/W
Port A PA[1] interrupt mask
0
MaskIRQPA[0]
0
R/W
Port A PA[0] interrupt mask
Interrupt is not stored if the mask bit is 0.
Table 10.1.10 Register RegIRQMask2
Bit
Name
Reset
R/W
Description
3
MaskIRQHz1
0
R/W
Prescaler interrupt mask
2
MaskIRQHz32/8
0
R/W
Prescaler interrupt mask
1
MaskIRQBlink
0
R/W
Prescaler interrupt mask
0
MaskIRQBz
0
R/W
Melody timer interrupt mask
Interrupt is not stored if the mask bit is 0.
Table 10.1.11 Register RegIRQMask3
Bit
Name
Reset
R/W
Description
3
MaskIRQSerial
0
R/W
Serial interrupt mask
2
MaskIRQMSC
0
R/W
Millisecond counter int. mask
1
MaskIRQCount0
0
R/W
Counter interrupt mask
0
MaskIRQCntComp
0
R/W
Counter interrupt mask
Interrupt is not stored if the mask bit is 0
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