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| 型號： | EM6821TQ52B |
| 英文描述： | Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: 0°C to 70°C; Package: 8-EPSOIC |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 11/69頁 |
| 文件大小： | 852K |
| 代理商： | EM6821TQ52B |
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EM6821
10/01, Revision A/386
Copyright
2001, EM Microelectronic-Marin SA
19
www.emmicroelectronic.com
6.4.4 PWM and Frequency Output
PB[3] can also be used to output the PWM (Pulse Width Modulation) signal from the 10-Bit Counter, the
Ck[16], Ck[11] as well as the Ck[1] prescaler frequencies.
-Selecting PWM output on PB[3] with bit PWMOn in register RegPresc and running the counter.
-Selecting Ck[16] output on PB[2] with bit PB32kHzOut in register OPTFSelPB
-Selecting Ck[11] output on PB[1] with bit PB1kHzOut in register OPTFSelPB
-Selecting Ck[1 ]
output on PB[0] with bit PB1HzOut
in register OPTFSelPB
6.5 Port B Registers
Table 6.5.1 Register RegPBData
Bit
Name
Reset
R/W
Description
3
PBData[3]
-
R*/W
PB[3] input and output
2
PBData[2]
-
R*/W
PB[2] input and output
1
PBData[1]
-
R*/W
PB[1] input and output
0
PBData[0]
-
R*/W
PB[0] input and output
* : Direct read on the port B terminal (not the internal register)
Table 6.5.2 Register RegPBCntl
Bit
Name
Reset
R/W
Description
3
PBIOCntl[3]
0
R/W
I/O control for PB[3]
2
PBIOCntl[2]
0
R/W
I/O control for PB[2]
1
PBIOCntl[1]
0
R/W
I/O control for PB[1]
0
PBIOCntl[0]
0
R/W
I/O control for PB[0]
Default "0" is: port B in input mode
Table 6.5.3 Option Register OPTFSelPB
Bit
Name
power on
value
R/W
Description
3
InpResSleep
0
R/W
Reset from sleep with port A
2
PB32kHzOut
0
R/W
Ck[16] output on PB[2]
1
PB1kHzOut
0
R/W
Ck[11] output on PB[1]
0
PB1HzOut
0
R/W
Ck[1] output on PB[0]
Default "0" is: No frequency output, port A Input Reset can not reset the SLEEP mode.
Table 6.5.4 Option Register OPTNoPdPB
Bit
Name
power on
value
R/W
Description
3
NoPdPB[3]
0
R/W
No pull-down on PB[3]
2
NoPdPB[2]
0
R/W
No pull-down on PB[2]
1
NoPdPB[1]
0
R/W
No pull-down on PB[1]
0
NoPdPB[0]
0
R/W
No pull-down on PB[0]
Default "0" is: Pull-down on
Table 6.5.5 Option Register OPTNchOpDPB
Bit
Name
power on
value
R/W
Description
3
NchOpDPB[3]
0
R/W
Nch. Open Drain on PB[3]
2
NchOpDPB[2]
0
R/W
Nch. Open Drain on PB[2]
1
NchOpDPB[1]
0
R/W
Nch. Open Drain on PB[1]
0
NchOpDPB[0]
0
R/W
Nch. Open Drain on PB[0]
Default "0" is: CMOS output
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