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參數(shù)資料
| 型號(hào)： | EM6821TQ52B |
| 英文描述： | Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: 0°C to 70°C; Package: 8-EPSOIC |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 38/69頁 |
| 文件大?。?/td> | 852K |
| 代理商： | EM6821TQ52B |
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EM6821
10/01, Revision A/386
Copyright
2001, EM Microelectronic-Marin SA
43
www.emmicroelectronic.com
11. Supply Voltage Level Detector
The EM6821 has a built-in Supply Voltage Level Detector (SVLD) circuitry, such that the CPU can compare the
supply voltage against a pre-selected value. During sleep mode this function is inhibited.
The CPU activates the supply voltage level
detector by writing VldStart = 1 in the register
RegVldCntl
. The actual measurement starts on
the next Ck[9] rising edge and lasts during the
Ck[9] high period (2 ms at 32 KHz). The busy
flag VldBusy stays high from VldStart set until
the measurement is finished. The worst case
time until the result is available is 1.5 Ck[9]
prescaler clock periods (32 KHz -> 6 ms). The
detection level must be defined in register
RegVldLevel
before the VldStart bit is set.
During the actual measurement (2 ms) the
device will draw an additional 5 A of IVDD
current. After the end of the measure the result
is available by inspection of the bit VldResult.
If the result is read 0, then the power supply
voltage was greater than the detection level value. If read 1, the power supply voltage was lower than the
detection level value. During each read while Busy=1 the VldResult is not guaranteed.
11.1 SVLD Register
Table 11.1.1 Register RegVldCntl
Bit
Name
Reset
R/W
Description
3
VldResult
0
R*
Vld result flag
2
VldStart
0
W
Vld start
2
VldBusy
0
R
Vld busy flag
1
NoOscWD
0
R/W
No Oscillator watchdog
0
NoLogicWD
0
R/W
No logic watchdog
R*; Read value while VLDBusy=1 is not guaranteed.
Table 11.1.2 Register RegVldLevel (Detection Level Value)
Bit
Name
Reset
R/W
Description
3
--
x
--
not active
2
VldLevel2
0
R/W
Vld level selection
1
VldLevel1
0
R/W
Vld level selection
0
VldLevel0
0
R/W
Vld level selection
Table 11.1.3 Voltage Level Detector Value Selecting
VldLevel2
VldLevel1
VldLevel0
Typical voltage level
Level1
0
4.0
Level2
0
1
3.0
Level3
0
1
0
2.4
Level4
0
1
2.0
Level5
1
0
1.75
Level6
1
0
1
1.5
Level7
1
0
1.35
Level8
1
1,20
Figure 32. SVLD Timing Diagram
VBAT =VDD
Compare Level
Ck[9] (256 Hz)
CPU starts
measure
Busy Flag
Measure
1
0
Result
Read Result
SVLD > VBAT
SVLD < VBAT
CPU starts
measure
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