參數(shù)資料
型號： DTMFDECODER-RD
廠商： Silicon Laboratories Inc
文件頁數(shù)： 59/178頁
文件大小： 0K
描述： KIT REF DESIGN DTMF DECODER
應用說明： DTMF Decoder Ref Design AppNote
標準包裝： 1
主要目的： 電信，DTMF 解碼器
嵌入式： 否
已用 IC / 零件： C8051F300
主要屬性： 8kHz 采樣速率模數(shù)轉(zhuǎn)換器
次要屬性： 16 個 Goertzel 濾波器
已供物品： 板，軟件
產(chǎn)品目錄頁面： 627 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： 336-1535-5-ND - IC 8051 MCU 8K FLASH 14-SOIC
C8051F300-GMR-ND - IC 8051 MCU 8K FLASH 11QFN
336-1245-ND - IC 8051 MCU 8K FLASH 11QFN
其它名稱： 336-1283
Rev. 2.9
151
C8051F300/1/2/3/4/5
15.2. Timer 2
Timer 2 is a 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines
the Timer 2 operation mode.
Timer 2 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the
internal oscillator drives the system clock while Timer 2 (and/or the PCA) is clocked by an external preci-
sion oscillator. Note that the external oscillator source divided by 8 is synchronized with the system clock.
15.2.1. 16-bit Timer with Auto-Reload
When T2SPLIT (TMR2CN.3) is zero, Timer 2 operates as a 16-bit timer with auto-reload. Timer 2 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 2
reload registers (TMR2RLH and TMR2RLL) is loaded into the Timer 2 register as shown in Figure 15.4,
and the Timer 2 High Byte Overflow Flag (TMR2CN.7) is set. If Timer 2 interrupts are enabled (if IE.5 is
set), an interrupt will be generated on each Timer 2 overflow. Additionally, if Timer 2 interrupts are enabled
and the TF2LEN bit is set (TMR2CN.5), an interrupt will be generated each time the lower 8 bits (TMR2L)
overflow from 0xFF to 0x00.
External Clock / 8
SYSCLK / 12
SYSCLK
TMR2L
TMR2H
TMR2RLL TMR2RLH
Reload
TCLK
0
1
TR2
TMR2
CN
T2SPLIT
TF2L
TF2H
T2XCLK
TR2
0
1
T2XCLK
CKCON
T
2
M
H
S
C
A
0
S
C
A
1
T
2
M
L
T
1
M
T
0
M
Interrupt
TF2LEN
To ADC,
SMBus
To SMBus
TMR2L
Overflow
Figure 15.4. Timer 2 16-Bit Mode Block Diagram
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