參數(shù)資料
型號： DTMFDECODER-RD
廠商： Silicon Laboratories Inc
文件頁數(shù)： 173/178頁
文件大?。?/td> 0K
描述： KIT REF DESIGN DTMF DECODER
應(yīng)用說明： DTMF Decoder Ref Design AppNote
標準包裝： 1
主要目的： 電信，DTMF 解碼器
嵌入式： 否
已用 IC / 零件： C8051F300
主要屬性： 8kHz 采樣速率模數(shù)轉(zhuǎn)換器
次要屬性： 16 個 Goertzel 濾波器
已供物品： 板，軟件
產(chǎn)品目錄頁面： 627 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： 336-1535-5-ND - IC 8051 MCU 8K FLASH 14-SOIC
C8051F300-GMR-ND - IC 8051 MCU 8K FLASH 11QFN
336-1245-ND - IC 8051 MCU 8K FLASH 11QFN
其它名稱： 336-1283
C8051F300/1/2/3/4/5
94
Rev. 2.9
10.4. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of VDD, system clock frequency, or temperature. This accidental execution of Flash modi-
fying code can result in alteration of Flash memory contents causing a system failure that is only recover-
able by re-Flashing the code in the device.
The following guidelines are recommended for any system which contains routines which write or erase
Flash from code.
10.4.1. VDD Maintenance and the VDD monitor
1.
If the system power supply is subject to voltage or current "spikes," add sufficient transient
protection devices to the power supply to ensure that the supply voltages listed in the Absolute
Maximum Ratings table are not exceeded.
2.
Make certain that the minimum VDD rise time specification of 1 ms is met. If the system cannot
meet this rise time specification, then add an external VDD brownout circuit to the RST pin of
the device that holds the device in reset until VDD reaches 2.7 V and re-asserts RST if VDD
drops below 2.7 V.
3.
Enable the on-chip VDD monitor and enable the VDD monitor as a reset source as early in code
as possible. This should be the first set of instructions executed after the Reset Vector. For 'C'-
based systems, this will involve modifying the startup code added by the 'C' compiler. See your
compiler documentation for more details. Make certain that there are no delays in software
between enabling the VDD monitor and enabling the VDD monitor as a reset source. Code
examples showing this can be found in “AN201: Writing to Flash from Firmware", available
from the Silicon Laboratories web site.
4.
As an added precaution, explicitly enable the VDD monitor and enable the VDD monitor as a
reset source inside the functions that write and erase Flash memory. The VDD monitor enable
instructions should be placed just after the instruction to set PSWE to a '1', but before the
Flash write or erase operation instruction.
5.
Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment
operators and explicitly DO NOT use the bit-wise operators (such as AND or OR). For exam-
ple, "RSTSRC = 0x02" is correct. "RSTSRC |= 0x02" is incorrect.
6.
Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a '1'. Areas
to check are initialization code which enables other reset sources, such as the Missing Clock
Detector or Comparator, for example, and instructions which force a Software Reset. A global
search on "RSTSRC" can quickly verify this.
10.4.2. PSWE Maintenance
7.
Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a '1'. There
should be exactly one routine in code that sets PSWE to a '1' to write Flash bytes and one rou-
tine in code that sets PSWE and PSEE both to a '1' to erase Flash pages.
8.
Minimize the number of variable accesses while PSWE is set to a '1'. Handle pointer address
updates and loop variable maintenance outside the "PSWE = 1; ... PSWE = 0;" area. Code
examples showing this can be found in AN201, "Writing to Flash from Firmware", available
from the Silicon Laboratories web site.
9.
Disable interrupts prior to setting PSWE to a '1' and leave them disabled until after PSWE has
been reset to '0'. Any interrupts posted during the Flash write or erase operation will be ser-
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