參數(shù)資料
型號： DTMFDECODER-RD
廠商： Silicon Laboratories Inc
文件頁數(shù)： 164/178頁
文件大?。?/td> 0K
描述： KIT REF DESIGN DTMF DECODER
應用說明： DTMF Decoder Ref Design AppNote
標準包裝： 1
主要目的： 電信，DTMF 解碼器
嵌入式： 否
已用 IC / 零件： C8051F300
主要屬性： 8kHz 采樣速率模數(shù)轉換器
次要屬性： 16 個 Goertzel 濾波器
已供物品： 板，軟件
產品目錄頁面： 627 (CN2011-ZH PDF)
相關產品： 336-1535-5-ND - IC 8051 MCU 8K FLASH 14-SOIC
C8051F300-GMR-ND - IC 8051 MCU 8K FLASH 11QFN
336-1245-ND - IC 8051 MCU 8K FLASH 11QFN
其它名稱： 336-1283
C8051F300/1/2/3/4/5
86
Rev. 2.9
9.7.
Flash Error Reset
If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:
A Flash write or erase is attempted above user code space. This occurs when PSWE is set to ‘1’ and a
MOVX operation is attempted above the user code space address limit.
A Flash read is attempted above user code space. This occurs when a MOVC operation is attempted
above the user code space address limit.
A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above the user code space address limit.
Table 9.1. User Code Space Address Limits
Device
User Code Space Address Limit
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by
this reset.
9.8.
Software Reset
Software may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will read ‘1’ fol-
lowing a software forced reset. The state of the RST pin is unaffected by this reset.
Table 9.2. Reset Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
RST Output Low Voltage
IOL = 8.5 mA, VDD = 2.7 V to
3.6 V
—
0.6
V
RST Input High Voltage
0.7 x VDD
—
V
RST Input Low Voltage
—
0.3 x VDD
RST Input Leakage Current
RST = 0.0 V
—
25
40
A
VDD Monitor Threshold (VRST)
2.40
2.55
2.70
V
Missing Clock Detector Timeout
Time from last system clock ris-
ing edge to reset initiation
100
220
500
s
Reset Time Delay
Delay between release of any
reset source and code execution
at location 0x0000
5.0
—
s
Minimum RST Low Time to
Generate a System Reset
15
—
s
VDD Ramp Time
VDD = 0 to VRST
—
1
ms
C8051F300/1/2/3
0x1DFF
C8051F304
0x0FFF
C8051F305
0x07FF
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