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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | DTMFDECODER-RD |
| 寤犲晢锛� | Silicon Laboratories Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 163/178闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | KIT REF DESIGN DTMF DECODER |
| 鎳�(y墨ng)鐢ㄨ鏄庯細 | DTMF Decoder Ref Design AppNote |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 涓昏鐩殑锛� | 闆讳俊锛孌TMF 瑙ｇ⒓鍣� |
| 宓屽叆寮忥細 | 鍚� |
| 宸茬敤 IC / 闆朵欢锛� | C8051F300 |
| 涓昏灞€э細 | 8kHz 閲囨ǎ閫熺巼妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 |
| 娆¤灞€э細 | 16 鍊� Goertzel 婵炬尝鍣� |
| 宸蹭緵鐗╁搧锛� | 鏉匡紝杌熶欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 627 (CN2011-ZH PDF) |
| 鐩搁棞(gu膩n)鐢�(ch菐n)鍝侊細 | 336-1535-5-ND - IC 8051 MCU 8K FLASH 14-SOIC C8051F300-GMR-ND - IC 8051 MCU 8K FLASH 11QFN 336-1245-ND - IC 8051 MCU 8K FLASH 11QFN |
| 鍏跺畠鍚嶇ū锛� | 336-1283 |
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Rev. 2.9
85
C8051F300/1/2/3/4/5
bit in register RSTSRC. See Figure 9.2 for VDD monitor timing; note that the reset delay is not incurred
Important Note: Enabling the VDD monitor will immediately generate a system reset. The device will then
return from the reset state with the VDD monitor enabled. Writing a logic 鈥�1鈥� to the PORSF flag when the
VDD monitor is enabled does not cause a system reset.
9.3.
External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 9.2 for complete RST pin spec-
ifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
9.4.
Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than 100 s, the one-shot will time out and generate a reset. After a
MCD reset, the MCDRSF flag (RSTSRC.2) will read 鈥�1鈥�, signifying the MCD as the reset source; otherwise,
this bit reads 鈥�0鈥�. Writing a 鈥�1鈥� to the MCDRSF bit enables the Missing Clock Detector; writing a 鈥�0鈥� disables
it. The state of the RST pin is unaffected by this reset.
9.5.
Comparator0 Reset
Comparator0 can be configured as a reset source by writing a 鈥�1鈥� to the C0RSEF flag (RSTSRC.5).
Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on
chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-
inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0鈥�), the device is put into
the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 鈥�1鈥� signifying
Comparator0 as the reset source; otherwise, this bit reads 鈥�0鈥�. The state of the RST pin is unaffected by
this reset.
9.6.
PCA Watchdog Timer Reset
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be
used to prevent software from running out of control during a system malfunction. The PCA WDT function
can be enabled or disabled by software as described in Section 鈥�16.3. Watchdog Timer Mode鈥� on
page 164; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction
prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is
set to 鈥�1鈥�. The state of the RST pin is unaffected by this reset.
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| DTMH04-2PC | 鍒堕€犲晢:TE Connectivity / Deutsch 鍔熻兘鎻忚堪:RECEPTACLE DTM HI TEMP C KEY 2WAY 鍒堕€犲晢:TE Connectivity / Deutsch 鍔熻兘鎻忚堪:RECEPTACLE, DTM HI TEMP, C KEY, 2WAY 鍒堕€犲晢:TE Connectivity / Deutsch 鍔熻兘鎻忚堪:RECEPTACLE, DTM HI TEMP, C KEY, 2WAY; Series:DTMH; Gender:Receptacle; No. of Contacts:2; No. of Rows:1; Contact Gender:Pin; Connector Mounting:Cable; Connector Shell Size:-; Contact Termination:Crimp; Contact Material:Copper; Contact;RoHS Compliant: Yes |
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