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參數(shù)資料
| 型號(hào)： | DSP1629 |
| 英文描述： | TVS 400W 64V UNIDIRECT SMA |
| 中文描述： | DSP1629數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 8/126頁(yè) |
| 文件大?。?/td> | 1993K |
| 代理商： | DSP1629 |
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Data Sheet
March 2000
DSP1629 Digital Signal Processor
8
Lucent Technologies Inc.
4 Hardware Architecture
The DSP1629 device is a 16-bit, fixed-point program-
mable digital signal processor (DSP). The DSP1629
consists of a DSP1600 core together with on-chip mem-
ory and peripherals. Added architectural features give
the DSP1629 high program efficiency for signal coding
applications.
4.1 DSP1629 Architectural Overview
Figure 4 shows a block diagram of the DSP1629. The
following modules make up the DSP1629.
DSP1600 Core
The DSP1600 core is the heart of the DSP1629 chip.
The core contains data and address arithmetic units,
and control for on-chip memory and peripherals. The
core provides support for external memory wait-states
and on-chip, dual-port RAM and features vectored inter-
rupts and a trap mechanism.
Dual-Port RAM (DPRAM)
The DSP1629x16 contains 16 banks of zero wait-state
memory and the DSP1629x10 contains 10 banks of
zero wait-state memory. Each bank consists of 1K
16-bit words and has separate address and data ports
to the instruction/coefficient and data memory spaces.
A program can reference memory from either space.
The DSP1600 core automatically performs the required
multiplexing. If references to both ports of a single bank
are made simultaneously, the DSP1600 core automati-
cally inserts a wait-state and performs the data port ac-
cess first, followed by the instruction/coefficient port
access.
A program can be downloaded from slow, off-chip mem-
ory into DPRAM, and then executed without wait-states.
DPRAM is also useful for improving convolution perfor-
mance in cases where the coefficients are adaptive.
Since DPRAM can be downloaded through the JTAG
port, full-speed remote in-circuit emulation is possible.
DPRAM can also be used for downloading self-test
code via the JTAG port.
Read-Only Memory (ROM)
The DSP1629 contains 48K 16-bit words of zero wait-
state mask-programmable ROM for program and fixed
coefficients.
External Memory Multiplexer (EMUX)
The EMUX is used to connect the DSP1629 to external
memory and I/O devices. It supports read/write opera-
tions from/to instruction/coefficient memory (X memory
space) and data memory (Y memory space). The
DSP1600 core automatically controls the EMUX. In-
structions can transparently reference external memory
from either set of internal buses. A sequencer allows a
single instruction to access both the X and the Y exter-
nal memory spaces.
Clock Synthesis
The DSP powers up with a 1X input clock (CKI/CKI2) as
the source for the processor clock. An on-chip clock
synthesizer (PLL) can also be used to generate the sys-
tem clock for the DSP, which will run at a frequency mul-
tiple of the input clock. The clock synthesizer is
deselected and powered down on reset. For low-power
operation, an internally generated slow clock can be
used to drive the DSP. If both the clock synthesizer and
the internally generated slow clock are selected, the
slow clock will drive the DSP; however, the synthesizer
will continue to run.
The clock synthesizer and other programmable clock
sources are discussed in Section 4.12. The use of these
programmable clock sources for power management is
discussed in Section 4.13.
Bit Manipulation Unit (BMU)
The BMU extends the DSP1600 core instruction set to
provide more efficient bit operations on accumulators.
The BMU contains logic for barrel shifting, normaliza-
tion, and bit field insertion/extraction. The unit also con-
tains a set of 36-bit alternate accumulators. The data in
the alternate accumulators can be shuffled with the data
in the main accumulators. Flags returned by the BMU
mesh seamlessly with the DSP1600 conditional instruc-
tions.
Bit Input/Output (BIO)
The BIO provides convenient and efficient monitoring
and control of eight individually configurable pins. When
configured as outputs, the pins can be individually set,
cleared, or toggled. When configured as inputs, individ-
ual pins or combinations of pins can be tested for pat-
terns. Flags returned by the BIO mesh seamlessly with
conditional instructions.
Serial Input/Output Units (SIO and SIO2)
SIO and SIO2 offer asynchronous, full-duplex, double-
buffered channels that operate at up to 25 Mbits/s (for
20 ns instruction cycle in a nonmultiprocessor configu-
ration), and easily interface with other Lucent Technol-
ogies fixed-point DSPs in a multiple-processor
environment. Commercially available codecs and time-
division multiplex (TDM) channels can be interfaced to
the serial I/O ports with few, if any, additional compo-
nents. SIO2 is identical to SIO.
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