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參數(shù)資料
| 型號(hào)： | DSP1629 |
| 英文描述： | TVS 400W 64V UNIDIRECT SMA |
| 中文描述： | DSP1629數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 25/126頁(yè) |
| 文件大?。?/td> | 1993K |
| 代理商： | DSP1629 |
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Data Sheet
March 2000
DSP1629 Digital Signal Processor
Lucent Technologies Inc.
25
4 Hardware Architecture
(continued)
4.10 Timer
The interrupt timer is composed of the timerc (control)
register, the timer0 register, the prescaler, and the
counter itself. The timer control register (see Table 31,
timerc Register) sets up the operational state of the tim-
er and prescaler. The timer0 register is used to hold the
counter reload value (or period register) and to set the
initial value of the counter. The prescaler slows the
clock to the timer by a number of binary divisors to allow
for a wide range of interrupt delay periods.
The counter is a 16-bit down counter that can be loaded
with an arbitrary number from software. It counts down
to 0 at the clock rate provided by the prescaler. Upon
reaching 0 count, a vectored interrupt to program ad-
dress 0x10 is issued to the DSP1629, providing the in-
terrupt is enabled (bit 8 of inc and ins registers). The
counter will then either wait in an inactive state for an-
other command from software, or will automatically re-
peat the last interrupting period, depending upon the
state of the RELOAD bit in the timerc register.
When RELOAD is 0, the counter counts down from its
initial value to 0, interrupts the DSP1629, and then
stops, remaining inactive until another value is written to
the timer0 register. Writing to the timer0 register causes
both the counter and the period register to be written
with the specified 16-bit number. When RELOAD is 1,
the counter counts down from its initial value to 0, inter-
rupts the DSP1629, automatically reloads the specified
initial value from the period register into the counter,
and repeats indefinitely. This provides for either a single
timed interrupt event or a regular interrupt clock of arbi-
trary period.
The timer can be stopped and started by software, and
can be reloaded with a new period at any time. Its count
value, at the time of the read, can also be read by soft-
ware. Due to pipeline stages, stopping and starting the
timer may result in one inaccurate count or prescaled
period. When the DSP1629 is reset, the bottom 6 bits of
the timerc register and the timer0 register and counter
are initialized to 0. This sets the prescaler to CKO/2*,
turns off the reload feature, disables timer counting, and
initializes the timer to its inactive state. The act of reset-
ting the chip does not cause a timer interrupt. Note that
the period register is not initialized on reset.
The T0EN bit of the timerc register enables the clock to
the timer. When T0EN is a 1, the timer counts down to-
wards 0. When T0EN is a 0, the timer holds its current
count.
*
Frequency of CKO/2 is equivalent to either CKI/2 for the PLL by-
passed or related to CKI by the PLL multiplying factors. See Sec-
tion 4.12, Clock Synthesis.
The PRESCALE field of the timerc register selects one
of 16 possible clock rates for the timer input clock (see
Table 31, timerc Register).
Setting the DISABLE bit of the timerc register to a logic
1 shuts down the timer and the prescaler for power sav-
ings. Setting the TIMERDIS, bit 4, in the powerc register
has the same effect of shutting down the timer. The
DISABLE bit and the TIMERDIS bit are cleared by writ-
ing a 0 to their respective registers to restore the normal
operating mode.
4.11 JTAG Test Port
The DSP1629 uses a JTAG/IEEE1149.1 standard five-
wire test port (TDI, TDO, TCK, TMS, TRST) for self-test
and hardware emulation. An instruction register, a
boundary-scan register, a bypass register, and a device
identification register have been implemented. The de-
vice identification register coding for the DSP1629 is
shown in Table 37. The instruction register (IR) is 4 bits
long. The instruction for accessing the device ID is 0xE
(1110). The behavior of the instruction register is sum-
marized in Table 10. Cell 0 is the LSB (closest to TDO).
The first line shows the cells in the IR that capture from
a parallel input in the capture-IR controller state. The
second line shows the cells that always load a logic 1 in
the capture-IR controller state. The third line shows the
cells that always load a logic 0 in the capture-IR control-
ler state. Cell 3 (MSB of IR) is tied to status signal PINT,
and cell 2 is tied to status signal JINT. The state of these
signals can therefore be captured during capture-IR and
shifted out during SHIFT-IR controller states.
Boundary-Scan Register
All of the chip's inputs and outputs are incorporated in a
JTAG scan path shown in Table 11. The types of
boundary-scan cells are as follows:
I
I = input cell
I
O = 3-state output cell
I
B = bidirectional (I/O) cell
I
OE = 3-state control cell
I
DC = bidirectional control cell
Table 10. JTAG Instruction Register
IR Cell #:
Parallel Input
Always Logic 1
Always Logic 0
3
Y
N
N
2
Y
N
N
1
N
N
Y
0
N
Y
N
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