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參數(shù)資料
| 型號(hào)： | DSP1629 |
| 英文描述： | TVS 400W 64V UNIDIRECT SMA |
| 中文描述： | DSP1629數(shù)字信號(hào)處理器 |
| 文件頁數(shù)： | 24/126頁 |
| 文件大?。?/td> | 1993K |
| 代理商： | DSP1629 |
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Data Sheet
March 2000
DSP1629 Digital Signal Processor
24
Lucent Technologies Inc.
4 Hardware Architecture
(continued)
Finally, the assertion level of the output pins, PIBF and POBE, is controlled through bit 4, PFLAG. When PFLAG is
set low, PIBF and POBE output pins have positive assertion levels. By setting bit 5, PFLAGSEL, the logical OR of
PIBF and POBE flags (positive assertion) is seen at the output pin PIBF. By setting bit 7 in phifc, PSOBEF, the po-
larity of the POBE flag in the status register, PSTAT, can be changed. PSOBEF has no effect on the POBE pin.
Pin Multiplexing
Please refer to Pin Multiplexing in Section 4.1 for a description of BIO, PHIF, VEC[3:0], and SIO2 pins.
Table 7. PHIF Function (8-bit and 16-bit Modes)
PMODE Field
0 (8-bit)
0
0
0
1 (16-bit)
1
1
1
PSTAT Pin
0
0
1
1
0
0
1
1
PBSEL Pin
0
1
0
1
0
1
0
1
PBSELF Field = 0
pdx0 low byte
reserved
PSTAT
reserved
pdx0 low byte
pdx0 high byte
PSTAT
reserved
PBSELF Field = 1
reserved
pdx0 low byte
reserved
PSTAT
pdx0 high byte
pdx0 low byte
reserved
PSTAT
Table 8. pstat Register as Seen on PB[7:0]
Bit
7
Field
6
5
4
3
2
1
0
RSVD
PIBF
POBE
4.9 Bit Input/Output Unit (BIO)
The BIO controls the directions of eight bidirectional
control I/O pins, IOBIT[7:0]. If a pin is configured as an
output, it can be individually set, cleared, or toggled. If a
pin is configured as an input, it can be read and/or test-
ed.
The lower half of the sbit register (see Table 33) con-
tains current values (VALUE[7:0]) of the eight bidirec-
tional pins IOBIT[7:0]. The upper half of the sbit register
(DIREC[7:0]) controls the direction of each of the pins.
A logic 1 configures the corresponding pin as an output;
a logic 0 configures it as an input. The upper half of the
sbit register is cleared upon reset.
The cbit register (see Table 34) contains two 8-bit fields,
MODE/MASK[7:0] and DATA/PAT[7:0]. The values of
DATA/PAT[7:0] are cleared upon reset. The meaning of
a bit in either field depends on whether it has been con-
figured as an input or an output in sbit. If a pin has been
configured to be an output, the meanings are MODE
and DATA. For an input, the meanings are MASK and
PAT (pattern). Table 9 shows the functionality of the
MODE/MASK and DATA/PAT bits based on the direc-
tion selected for the associated IOBIT pin.
Those bits that have been configured as inputs can be
individually tested for 1 or 0. For those inputs that are
being tested, there are four flags produced: allt (all true),
allf (all false), somet (some true), and somef (some
false). These flags can be used for conditional branch or
special instructions. The state of these flags can be
saved and restored by reading and writing bits 0 to 3 of
the alf register (see Table 35).
If a BIO pin is switched from being configured as an out-
put to being configured as an input and then back to be-
ing configured as an output, the pin retains the previous
output value.
Pin Multiplexing
Please refer to Pin Multiplexing in Section 4.1 for a
description of BIO, PHIF, VEC[3:0], and SIO2 pins.
Table 9. BIO Operations
DIREC[n]
*
* 0
≤
n
≤
7.
MODE/
MASK[n]
0
0
1
1
0
0
1
1
DATA/
PAT[n]
0
1
0
1
0
1
0
1
Action
1 (Output)
1 (Output)
1 (Output)
1 (Output)
0 (Input)
0 (Input)
0 (Input)
0 (Input)
Clear
Set
No Change
Toggle
No Test
No Test
Test for Zero
Test for One
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