參數(shù)資料
型號(hào): DSP1629
英文描述: TVS 400W 64V UNIDIRECT SMA
中文描述: DSP1629數(shù)字信號(hào)處理器
文件頁數(shù): 115/126頁
文件大小: 1993K
代理商: DSP1629
Data Sheet
March 2000
DSP1629 Digital Signal Processor
Lucent Technologies Inc.
115
11 Timing Characteristics for 2.7 V Operation
(continued)
Figure 52. PHIF, PIBF, and POBE Reset Timing Diagram
*
After reset, POBE and PIBF always go to the levels shown, indicating output buffer empty and input buffer empty. The DSP program, however,
may later invert the definition of the logic levels for POBE and PIBF. t57 and t58 continue to apply.
POBE and PIBF can be programmed to be active-high or active-low. They are shown active-high. The timing characteristic for active-low is
the same as for active-high
.
Figure 53. PHIF, PIBF, and POBE Disable Timing Diagram
Table 134. PHIF Timing Characteristics for PHIF, PIBF, and POBE Reset
Abbreviated Reference
t57
t58
Parameter
Min
3
Max
25
25
Unit
ns
ns
RSTB Disable to POBE/PIBF* (high to valid)
RSTB Enable to POBE/PIBF* (low to invalid)
Table 135. PHIF Timing Characteristics for POBE and PIBF Disable
Abbreviated Reference
t59
Parameter
Min
Max
20
Unit
ns
CKO to POBE/PIBF Disable (high/low to disable)
RSTB
V
IH
V
IL
t58
t57
POBE
V
OH
V
OL
PIBF
V
OH
V
OL
5-4775 (F)
CKO
V
IH
V
IL
t59
t59
POBE
V
OH
V
OL
PIBF
V
OH
V
OL
5-4776 (F)
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