
Data Sheet
March 2000
DSP1629 Digital Signal Processor
Lucent Technologies Inc.
55
5 Software Architecture
(continued)
Table 39. powerc Register
Note: The reserved (RSVD) bits should always be written with zeros to make the program compatible with future chip versions.
A
indicates that this bit is unknown on powerup reset and unaffected on subsequent reset. An S indicates that this
bit shadows the PC. P indicates the value on an input pin, i.e., the bit in the register reflects the value on the corre-
sponding input pin.
If EXM is high and INT1 is low when RSTB goes high,
mwait
will contain all ones instead of all zeros.
The
powerc
register configures various power management modes.
Bit
Field
XTLOFF SLOWCKI NOCK INT0EN RSVD INT1EN RSVD SIO1DIS SIO2DIS PHIFDIS TIMERDIS RSVD
15
14
13
12
11
10
9—8
7
6
5
4
3—0
powerc fields
Field
XTLOFF
SLOWCKI
NOCK
INT0EN
INT1EN
SIO1DIS
SIO2DIS
PHIFDIS
TIMERDIS
Description
1 = powerdown small-signal clock input.
1 = select ring oscillator clock (internal slow clock).
1 = disable internal processor clock.
1 = INT0 clears NOCK field.
1 = INT1 clears NOCK field.
1 = disable SIO1.
1 = disable SIO2.
1 = disable PHIF.
1 = disable timer.
Table 40. Register Settings After Reset
Register
r0
r1
r2
r3
j
k
rb
re
pt
pr
pi
i
p
pl
x
y
yl
auc
psw
c0
c1
c2
sioc
srta
sdx
tdms
phifc
pdx0
ybase
Bits 15—0
0000000000000000
0000000000000000
SSSSSSSSSSSSSSSS
0000000000000000
00
0000000000
0000000000
0000000000000000
0000000000000000
Register
inc
ins
sdx2
saddx
cloop
mwait
saddx2
sioc2
cbit
sbit
ioc
jtag
Bits 15—0
0000000000000000
0000010000000110
000000000
0000000000000000
0000000000
00000000PPPPPPPP
0000000000000000
a0
a0l
a1
a1l
00000000
0000000000000000
0000000000
0000000000000000
0000000000000000
timerc
timer0
tdms2
srta2
powerc
pllc
ar0
ar1
ar2
ar3
alf
00000000