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參數(shù)資料
| 型號(hào)： | DS34S132GN+ |
| 廠(chǎng)商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 139/194頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TDM OVER PACKET 676-BGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 功能： | TDM-over-Packet（TDMoP） |
| 接口： | TDMoP |
| 電路數(shù)： | 1 |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-PBGA（27x27） |
| 包裝： | 管件 |
| 其它名稱(chēng)： | 90-34S13+2N0 |
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DS34S132 DATA SHEET
19-4750; Rev 1; 07/11
49 of 194
minimum to its maximum value, a small number of packets are discarded and the latency is reduced to “PDV +
PCT”. You could say that this approach assumes the PDV = 0 for the first packet. The maximum number of packets
that will be discarded during the life of the connection will be the Integer value of (PDV ÷ PCT) + 1 (e.g. if PDV = 10
ms and PCT = 2 ms, then up to 6 packets may be discarded). The discard timing is not predictable since the
discarding only occurs when the PDV extremes are reached. The settings for this approach are specified by:
PDVT2 (in ms) = Total PDV (in ms)
MJBS2 (in ms) = PCT (in ms) + Total PDV (in ms)
The third approach also assumes that the delay and data errors must be minimized but also prevents the latency
from exceeding “PDV + PCT”. Instead of allowing for a small number of packet discards, this approach allows for a
small amount of dummy data insertion. The Jitter Buffer immediately forwards the first data is received, as though
the packet is assumed to be received with maximum PDV. Since this will not normally be the case, a Jitter Buffer
underrun will be expected. However, the amount of dummy data that is inserted (to stabilize the Jitter Buffer fill
level) is limited by the Total PDV value. For example if PDV = 10 ms and PCT = 2 ms, then ≤ 12 ms of dummy data
may be transmitted. The timing of the dummy data is not predictable since the insertion of dummy data depends on
when the PDV extremes are reached. The settings for this approach are specified by the following equations:
PDVT3 = 0x0001 (minimum setting > 0)
MJBS3 (in ms) = PCT (in ms) + Total PDV (in ms)
The PDVT and MJBS values are programmed using the equations below and should be rounded up to the nearest
integer setting. The units used by these registers vary according to the application:
PDVT setting units for T1/E1 CES: 125, 250 or 500 us (according to the Pn.PTCR1.BFD setting)
PDVT setting units for SAT: 32 ÷ “TDM Port bit rate” (e.g. the T1 SAT PDVT setting is in 20.7 us steps)
MJBS setting units for T1/E1 CES: 500 us
MJBS setting units for SAT: 1024 ÷ “TDM Port bit rate” (e.g. the E1 SAT PDVT setting is in 500 us steps)
The Jitter Buffer Fill Level impacts the total delay of the reconstructed TDM data stream. The fill level of the Jitter
Buffer is constantly changing according to the bursty nature of the RXP packets. So the delay of a TDM data
stream is not referenced to when an RXP packet is received but is instead viewed as the delay from the receive
TDM Port at the far PW End Point to the transmit TDM Port at the near/local end.
If the Jitter Buffer can store enough data to equal (or exceed) the Total PDV, then the Total PDV can be viewed as
being included in the Maximum Jitter Buffer Fill Level. Because the Jitter Buffer fill level is constantly changing, it is
not easy to define an independent Jitter Buffer delay parameter (to calculate the total delay). But in general the
“highest” Jitter Buffer fill level can be equated to the “Jitter Buffer + Total PDV” delay (assuming Maximum Fill Level
≥ Total PDV). The term “highest” is used, because it is possible that the Jitter Buffer fill level will stabilize at a level
that is lower than the programmed Maximum Fill Level (e.g. the Jitter Buffer “highest” fill level may stabilize at a 6
ms level, while MJBS may be programmed to 8 ms). Although the Jitter Buffer for a PW may stabilize below the
Maximum Fill Level, the total delay is most commonly estimated with the equation below:
Max Total Delay PCT + fixed transmission delay + TXP BFD + Max Jitter Buffer Fill Level
For a T1 SAT PW and assuming PCT = 1 ms, fixed transmission delay = 2.5 ms (e.g. 500 km fiber), Network PDV
= 3 ms and the remaining PDV = 910 us (from the previous Total PDV example), the 3 approaches will result in:
Approach #1 (No Data Discard)
PDVT1 (in ms) = 2 * 3.91 ms = 7.82 ms (PDVT1 register = 0x017A or 378 decimal which equates to 7.82 ms)
MJBS1 (in ms) = 1 ms + 7.82 ms = 8.82 ms (MJBS1 register = 0x0012 or 18 decimal which equates to 9 ms)
Max Total Delay1 = 1 ms + 2.5 ms + 9 ms = 12.5 ms (assuming MJBS is used to discard data)
Approach #2 (Minimize Delay With Limited Overrun)
PDVT2 (in ms) = 3.91 ms (PDVT2 register = 0x00BD or 189 decimal which equates to 3.91 ms)
MJBS2 (in ms) = 1 ms + 3.91 ms = 4.91 ms (MJBS2 register = 0x000A or 10 decimal which equates to 5 ms)
Max Total Delay2 = 1 ms + 2.5 ms + 5 ms = 8.5 ms (assuming MJBS is used to discard data)
For this approach the initial Max Total Delay may be as much as 1 + 2.5 + 2 * 5 = 13.5 ms, but will drop to Max
Total Delay = 8.5 ms after packets have been discarded due to Jitter Buffer overrun events.
Approach #3 (Minimize Delay With Limited Underrun)
PDVT3 (in ms) = 0 ms (PDVT3 register = 0x0001 which equates to 20.7 us)
MJBS3 (in ms) = 1 ms + 3.91 ms = 4.91 ms (MJBS3 register = 0x000A or 10 decimal which equates to 5 ms)
Max Total Delay3 = 1 ms + 2.5 ms + 5 ms = 8.5 ms (assuming MJBS is used to discard data)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| DS34S132GN+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類(lèi)型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34S132GNA2+ | 功能描述:通信集成電路 - 若干 32Port TDM-Over-Pack Transport Device RoHS:否 制造商:Maxim Integrated 類(lèi)型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據(jù)速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
| DS34T101 | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_08 | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
| DS34T101_09 | 制造商:MAXIM 制造商全稱(chēng):Maxim Integrated Products 功能描述:Single/Dual/Quad/Octal TDM-over-Packet Chip |
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