
DS34S132 DATA SHEET
19-4750; Rev1; 7/11
22 of 194
8.2 Detailed Pin Descriptions
Table 8-2. Detailed Pin Descriptions
Pin Name
Type Pin Description
TDM Port n = 0 through 31 Ports
TCLKOn
Oz
Transmit Clock Output. TCLKOn is derived from the clock recovery engine or from
RCLKn when in loop-timed mode or from the EXTCLK signal.
TSYNCn
IO
Transmit Sync. TSYNCn may be a frame or multi-frame input or output signal. Each
frame is a 125 us time period. The frame count for each multi-frame type is: T1-SF =
12; T1-ESF = 24; E1 = 16. If configured as an input, it is sampled by TCLKOn. If
configured as an output, it is output with respect to TCLKOn.
TDATn
Oz
Transmit Data Output. TDATn is the TDM datastream recovered from the PSN,
output with respect to TCLKOn.
TSIGn
Oz
Transmit Signaling. TSIGn is the transmit signaling recovered from the PSN, output
with respect to TCLKOn. The CAS values are updated once every TSYNC period.
RCLKn
I
Receive Clock. RCLKn is input clock typically derived from a T1/E1 framer or LIU.
RSYNCn
I
Receive Sync. RSYNCn indicates the frame or multi-frame boundary for the T1/E1
datastream, typically derived from a T1/E1 framer or LIU and sampled by RCLKn.
Each frame is a 125 us period. The frame count for each multi-frame type is: T1-SF =
12; T1-ESF = 24; E1 = 16.
RDATn
I
Receive Data. RDATn is the receive TDM datastream typically derived from a T1/E1
framer or LIU, sampled by RCLKn.
RSIGn
I
Receive Signaling. RSIGn is the receive signaling typically derived from a T1/E1
framer, sampled by RCLKn. The CAS values are updated once every RSYNC period.
100/1000 Mbps Ethernet MAC Interface (GMII/MII)
TXCLK
Ipu
Transmit Clock (MII). Timing reference for TXEN and TXD[0:3]. The TXCLK
frequency is 25 MHz for 100 Mbit/s operation.
GTXCLK
Oz
GMII Transmit Clock Output. 125MHz clock output available for GMII operation.
This clock is synchronous to ETHCLK input.
TXD[0:7]
Oz
Transmit Data 0 through 7(GMII Mode – TXD[0:7]). TXD[0:7] is presented
synchronously with the rising edge of TXCLK. TXD[0] is the least significant bit of the
data. When TXEN is low the data on TXD should be ignored.
Transmit Data 0 through 3(MII Mode – TXD[0:3]). Four bits of data TXD[0:3]
presented synchronously with the rising edge of TXCLK. When MII mode is selected,
TXD[4:7] pins are not used.
TXEN
Oz
Transmit Enable (GMII). When this signal is asserted, the data on TXD[0:7] is valid;
synchronous with GTXCLK.
Transmit Enable (MII). In MII mode, this pin is asserted high when data TXD[0:3] is
being provided by the device. This signal is synchronous with the rising edge TXCLK.
It is asserted with the first bit of the preamble. Synchronous with TXCLK.
TXER
Oz
Transmit Error (GMII, MII). When this signal is asserted, the PHY will respond by
sending one or more code groups in error.
RXCLK
Ipu
Receive Clock (GMII). 125 MHz clock. This clock is used to sample the RXD[0:7]
data.
Receive Clock (MII). Timing reference for RXDV, RXER and RXD[0:3], which are
clocked on the rising edge. RXCLK frequency is 25 MHz for 100 Mbit/s operation.