參數(shù)資料
型號： DS26303LN-75+A3
廠商： Maxim Integrated Products
文件頁數(shù)： 71/101頁
文件大?。?/td> 0K
描述： IC LIU E1/T1/J1 3.3V 144-ELQFP
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 1
類型： 線路接口裝置（LIU）
驅(qū)動器/接收器數(shù)： 8/8
規(guī)程： T1/E1/J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP 裸露焊盤
供應商設(shè)備封裝： 144-LQFP 裸露焊盤
包裝： 托盤
其它名稱： 90-26303+7N3
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
71 of 101
Figure 6-13. Repetitive Pattern Synchronization State Diagram
Sync
Match
Verify
1 bit error
Pattern Matches
32
bi
ts
w
it
ho
ut
er
ro
rs
6
of
64
bi
ts
w
ith
er
ro
rs
6.9.3.3
Receive Pattern Monitoring
Receive pattern monitoring monitors the incoming data stream for both an OOS condition and bit errors and counts
the incoming bits. An out-of-synchronization (OOS) condition is declared when the synchronization state machine
is not in the sync state. An OOS condition is terminated when the synchronization state machine is in the sync
state.
Bit errors are determined by comparing the incoming data stream bit to the receive pattern generator output. If they
do not match, a bit error is declared, and the bit error and bit counts are incremented. If they match, only the bit
count is incremented. The bit count and bit-error count are not incremented when an OOS condition exists.
6.9.4
Transmit Pattern Generation
Pattern generation generates the outgoing test pattern and passes it onto error insertion. The transmit pattern
generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or bit 1 to the most significant
bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern (generating polynomial x
n + xy + 1), the
feedback is an XOR of bit n and bit y. For a repetitive pattern (length n), the feedback is bit n. The values for n and
y are individually programmable (1 to 32). The output of the receive pattern generator is the feedback. If QRSS is
enabled, the feedback is an XOR of bits 17 and 20, and the output will be forced to one if the next 14 bits are all 0s.
QRSS is programmable (on or off). For PRBS and QRSS patterns, the feedback will be forced to 1 if bits 1 to 31
are all 0s. When a new pattern is loaded, the pattern generator is loaded with a seed/pattern value before pattern
generation starts. The seed/pattern value is programmable (0 – 2
n – 1).
6.9.4.1
Transmit Error Insertion
Error insertion inserts errors into the outgoing pattern data stream. Errors are inserted one at a time or at a rate of
one out of every 10
n bits. The value of n is programmable (1 to 7 or off). Single bit-error insertion can be initiated
from the microprocessor interface, or by the manual error-insertion input (TMEI). The method of single error
insertion is programmable (register or input). If pattern inversion is enabled, the data stream is inverted before the
overhead/stuff bits are inserted. Pattern inversion is programmable (on or off).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS26303LN-XXX 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
DS26303LN-XXX+ 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
DS26303L-XXX 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
DS26303L-XXX+ 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
DS26-32.768-STD-020 制造商:Micro Crystal Switzerland 功能描述:
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