參數(shù)資料
型號： DS26303LN-75+A3
廠商： Maxim Integrated Products
文件頁數(shù)： 11/101頁
文件大?。?/td> 0K
描述： IC LIU E1/T1/J1 3.3V 144-ELQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 1
類型： 線路接口裝置（LIU）
驅(qū)動器/接收器數(shù)： 8/8
規(guī)程： T1/E1/J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 144-LQFP 裸露焊盤
包裝： 托盤
其它名稱： 90-26303+7N3
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
17 of 101
NAME
PIN
TYPE
FUNCTION
A4/RIMPMSB
12
A3/GMC3
13
A2/GMC2
14
A1/GMC1
15
A0/GMC0
16
I
Address Bus 4–0/G.772 Monitoring Control/Rx Impedance
Mode Select
A[4:0]:
These five pins are address pins in parallel host mode. In
serial host mode and multiplexed host mode, these pins should be
grounded.
RIMPMSB:
In hardware mode when this pin is low, the internal
impedance mode is selected, so all RTIP and RING pins require
no external resistance component. When high, external
impedance mode is selected so all RTIP and RING pins require
external resistance.
GMC[3:0]:
In hardware mode, these signal pins are used to select
a transmit line (TTIPn/TRINGn) or receive line (RTIPn/RRINGn)
for nonintrusive monitoring. Receiver 1 is used to monitor
channels 2 to 8 See Table 5-9.
OE
114
I
Output Enable.
If this pin is pulled low, all the transmitter outputs
(TTIPn and TRINGn) are high impedance. Additionally, the user
may use this same pin to turn off all the impedance matching for
the receivers at the same time if register bit GMR.RHPMC is set.
CLKE
115
I
Clock Edge.
When CLKE is high, SDO is valid on the falling edge
of SCLK. When CLKE is low SDO is valid on the rising edge of
SCLK. When CLKE is high, the RCLKn for all the channels is
inverted. This aligns RPOSn/RNEGn on the falling edge of RCLKn
and overrides the settings in register RCLKI. When low,
RPOSn/RNEGn is aligned according to the settings in register
JTAG
JTRSTB
95
I, pullup
JTAG Test Port Reset.
This pin if low resets the JTAG port. If not
used it can be left floating.
JTMS
96
I, pullup
JTAG Test Mode Select.
This pin is clocked on the rising edge of
JTCLK and is used to control the JTAG selection between scan
and test machine control.
JTCLK
97
I
JTAG Test Clock.
The data JTDI and JTMS are clocked on rising
edge of JTCLK and JTDO is clocked out on the falling edge of
JTCLK.
JTDO
98
O,
high-Z
JTAG Test Data Out.
This is the serial output of the JTAG port.
The data is clocked out on the falling edge of JTCLK.
JTDI
99
I, pullup
Test Data Input.
This pin input is the serial data of the JTAG test.
The data on JTDI is clocked on the rising edge of JTCLK. This pin
can be left unconnected.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS26303LN-XXX 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
DS26303LN-XXX+ 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
DS26303L-XXX 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
DS26303L-XXX+ 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
DS26-32.768-STD-020 制造商:Micro Crystal Switzerland 功能描述:
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