參數(shù)資料
型號： DS26303LN-75+A3
廠商： Maxim Integrated Products
文件頁數(shù)： 48/101頁
文件大?。?/td> 0K
描述： IC LIU E1/T1/J1 3.3V 144-ELQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
類型： 線路接口裝置（LIU）
驅(qū)動器/接收器數(shù)： 8/8
規(guī)程： T1/E1/J1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 144-LQFP 裸露焊盤
包裝： 托盤
其它名稱： 90-26303+7N3
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
50 of 101
Register Name:
TEICR
Register Description:
Transmit Error-Insertion Control Register
Register Address:
08h
Bit #
7
6
5
4
3
2
1
0
Name
—
TEIR2
TEIR1
TEIR0
BEI
TSEI
MEIMS
Default
0
Bits 5 to 3: Transmit Error-Insertion Rate (TEIR[2:0]).
These bits indicate the rate at which errors are inserted in
the output data stream. One out of every 10
n bits is inverted. TEIR[2:0] is the value n. A TEIR[2:0] value of 0
disables error insertion at a specific rate. A TEIR[2:0] value of 1 result in every 10th bit being inverted. A TEIR[2:0]
value of 2 result in every 100th bit being inverted. Error insertion starts when this register is written to with a
TEIR[2:0] value that is non-zero. If this register is written to during the middle of an error insertion process, the new
error rate will be started after the next error is inserted.
Bit 2: Bit-Error-Insertion Enable (BEI).
When 0, single bit-error insertion is disabled. When 1, single bit-error
insertion is enabled.
Bit 1: Transmit Single Error Insert (TSEI).
This bit causes a bit error to be inserted in the transmit data stream if
manual error insertion is disabled (MEIMS = 0) and single bit-error insertion is enabled. A 0-to-1 transition causes a
single bit error to be inserted. For a second bit error to be inserted, this bit must be set to 0, and back to 1. Note: If
MEIMS is low, and this bit transitions more than once between error insertion opportunities, only one error is
inserted.
Bit 0: Manual-Error Insert-Mode Select (MEIMS).
When 0, error insertion is initiated by the TSEI register bit.
When 1, error insertion is initiated by the transmit manual-error-insertion signal (TMEI). Note: If TMEI or TSEI is 1,
changing the state of this bit may cause a bit error to be inserted.
Register Name:
BSR
Register Description:
BERT Status Register
Register Address:
0Ch
Bit #
7
6
5
4
3
2
1
0
Name
—
PMS
—
BEC
OOS
Default
0
Bit 3: Performance-Monitoring Update Status (PMS).
This bit indicates the status of the receive performance-
monitoring register (counters) update. This bit transitions from low to high when the update is completed. PMS is
asynchronously forced low when the LPMU bit (PMUM = 0) or RPMU signal (PMUM = 1) goes low.
Bit 1: Bit Error Count (BEC).
When 0, the bit error count is 0. When 1, the bit error count is 1 or more.
Bit 0: Out of Synchronization (OOS).
When 0, the receive pattern generator is synchronized to the incoming
pattern. When 1, the receive pattern generator is not synchronized to the incoming pattern.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS26303LN-XXX 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
DS26303LN-XXX+ 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
DS26303L-XXX 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
DS26303L-XXX+ 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
DS26-32.768-STD-020 制造商:Micro Crystal Switzerland 功能描述:
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