參數(shù)資料
型號: DS2154
廠商: Maxim Integrated Products, Inc.
英文描述: Enhanced E1 Single Chip Transceiver(改進(jìn)型E1單片收發(fā)器)
中文描述: 增強(qiáng)型E1單芯片收發(fā)器
文件頁數(shù): 48/71頁
文件大?。?/td> 654K
代理商: DS2154
DS2154
071498 48/71
Sa6
TSaCR.2
Additional Bit 6 Insertion Control Bit.
0=do not insert data from the TSa6 register into the transmit data stream
1=insert data from the TSa6 register into the transmit data stream
Sa7
TSaCR.1
Additional Bit 7 Insertion Control Bit.
0=do not insert data from the TSa7 register into the transmit data stream
1=insert data from the TSa7 register into the transmit data stream
Sa8
TSaCR.0
Additional Bit 8 Insertion Control Bit.
0=do not insert data from the
TSa8 register into the transmit data stream
1=insert data from the
TSa8 register into the transmit data stream
12.0 LINE INTERFACE FUNCTIONS
The line interface function in the DS2154 contains three
sections; (1) the receiver which handles clock and data
recovery, (2) the transmitter which waveshapes and
drives the E1 line, and (3) the jitter attenuator. Each of
the these three sections is controlled by the Line Inter-
face Control Register (LICR) which is described below.
LICR: LINE INTERFACE CONTROL REGISTER
(Address=18 Hex)
(MSB)
(LSB)
L2
L1
L0
EGL
JAS
JABDS
DJA
TPD
SYMBOL
POSITION
NAME AND DESCRIPTION
L2
LICR.7
Line Build Out Bit 2.
Transmit waveshape setting; see Table 12–2.
L1
LICR.6
Line Build Out Bit 1.
Transmit waveshape setting; see Table 12–2.
L0
LICR.5
Line Build Out Bit 0.
Transmit waveshape setting; see Table 12–2.
EGL
LICR.4
Receive Equalizer Gain Limit.
0=–12 dB
1=–43 dB
JAS
LICR.3
Jitter Attenuator Select.
0=place the jitter attenuator on the receive side
1=place the jitter attenuator on the transmit side
JABDS
LICR.2
Jitter Attenuator Buffer Depth Select
0=128–bits
1=32–bits (use for delay sensitive applications)
DJA
LICR.1
Disable Jitter Attenuator.
0=jitter attenuator enabled
1=jitter attenuator disabled
TPD
LICR.0
Transmit Power Down.
0=normal transmitter operation
1=powers down the transmitter and 3–states the TTIP and TRING pins
clock recovery system. The clock recovery system
uses the clock from the PLL circuit to form a 16 times
oversampler which is used to recover the clock and
data. This oversampling technique offers outstanding
jitter tolerance (see Figure 12–2).
12.1 RECEIVE CLOCK AND DATA
RECOVERY
The DS2154 contains a digital clock recovery system.
See the DS2154 Block Diagram in Section 1 and
Figure 12–1 for more details. The DS2154 couples to
the receive E1 shielded twisted pair or COAX via a 1:1
transformer. See Table 12–3 for transformer details.
The 2.048 MHz clock attached at the MCLK pin is inter-
nally multiplied by 16 via an internal PLL and fed to the
Normally, the clock that is output at the RCLKO pin is the
recovered clock from the E1 AMI/HDB3 waveform pres-
ented at the RTIP and RRING inputs. When no AMI sig-
LICR
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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DS2154L+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Enhanced E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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