參數(shù)資料
型號: DS2154
廠商: Maxim Integrated Products, Inc.
英文描述: Enhanced E1 Single Chip Transceiver(改進型E1單片收發(fā)器)
中文描述: 增強型E1單芯片收發(fā)器
文件頁數(shù): 19/71頁
文件大?。?/td> 654K
代理商: DS2154
DS2154
071498 19/71
IDR: DEVICE IDENTIFICATION REGISTER
(Address= 0F Hex)
(MSB)
(LSB)
T1E1
0
0
0
ID3
ID2
ID1
ID0
SYMBOL
POSITION
NAME AND DESCRIPTION
T1E1
IDR.7
T1 or E1 Chip Determination Bit.
0=T1 chip
1=E1 chip
ID3
IDR.3
Chip Revision Bit 3.
MSB of a decimal code that represents the chip revi-
sion.
ID2
IDR.1
Chip Revision Bit 2.
ID1
IDR.2
Chip Revision Bit 1.
ID0
IDR.0
Chip Revision Bit 0.
LSB of a decimal code that represents the chip revi-
sion.
RCR1: RECEIVE CONTROL REGISTER 1
(Address=10 Hex)
(MSB)
(LSB)
RSMF
RSM
RSIO
FRC
SYNCE
RESYNC
SYMBOL
POSITION
NAME AND DESCRIPTION
RSMF
RCR1.7
RSYNC Multiframe Function.
Only used if the RSYNC pin is pro-
grammed in the multiframe mode (RCR1.6=1).
0=RSYNC outputs CAS multiframe boundaries
1=RSYNC outputs CRC4 multiframe boundaries
RSM
RCR1.6
RSYNC Mode Select.
0=frame mode (see the timing in Section 13)
1=multiframe mode (see the timing in Section 13)
RSIO
RCR1.5
RSYNC I/O Select.
(note: this bit must be set to zero when RCR2.1=0).
0=RSYNC is an output (depends on RCR1.6)
1=RSYNC is an input (only valid if elastic store enabled)
RCR1.4
Not Assigned.
Should be set to zero when written.
RCR1.3
Not Assigned.
Should be set to zero when written.
FRC
RCR1.2
Frame Resync Criteria.
0=resync if FAS received in error 3 consecutive times
1=resync if FAS or bit 2 of non–FAS is received in error 3 consecutive times
SYNCE
RCR1.1
Sync Enable.
0=auto resync enabled
1=auto resync disabled
RESYNC
RCR1.0
Resync.
When toggled from low to high, a resync is initiated. Must be
cleared and set again for a subsequent resync.
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