參數(shù)資料
型號(hào): DS2154
廠商: Maxim Integrated Products, Inc.
英文描述: Enhanced E1 Single Chip Transceiver(改進(jìn)型E1單片收發(fā)器)
中文描述: 增強(qiáng)型E1單芯片收發(fā)器
文件頁(yè)數(shù): 24/71頁(yè)
文件大?。?/td> 654K
代理商: DS2154
DS2154
071498 24/71
RFE
CCR2.0
Receive Freeze Enable.
See Section 7–2 for details.
0=no freezing of receive signaling data will occur
1=allow freezing of receive signaling data at RSIG (and RSER if
CCR3.3=1).
AUTOMATIC ALARM GENERATION
When either CCR2.4 or CCR2.5 is set to one, the
DS2154 monitors the receive side to determine if any of
the following conditions are present: loss of receive
frame synchronization, AIS alarm (all one’s) reception,
or loss of receive carrier (or signal). If any one (or more)
of the above conditions is present, then the DS2154 will
either force an AIS alarm (if CCR2.5=1) or a Remote
Alarm (CCR2.4=1) to be transmitted via the TPOSO
and TNEGO pins. It is an illegal state to have both
CCR2.4 and CCR2.5 set to one at the same time. If
CCR2.4=1, then RAI will be transmitted according to
ETS 300 011 specifications and a constant Remote
Alarm will be transmitted if the DS2154 cannot find
CRC4 multiframe synchronization within 400 ms as per
G.706.
CCR3: COMMON CONTROL REGISTER 3
(Address=1B Hex)
(MSB)
(LSB)
TESE
TCBFS
TIRFS
ESR
RSRE
THSE
TBCS
RCLA
SYMBOL
POSITION
NAME AND DESCRIPTION
TESE
CCR3.7
Transmit Side Elastic Store Enable.
0=elastic store is bypassed
1=elastic store is enabled
TCBFS
CCR3.6
Transmit Channel Blocking Registers (TCBR) Function Select.
0=TCBRs define the operation of the TCHBLK output pin
1=TCBRs define which signaling bits are to be inserted
TIRFS
CCR3.5
Transmit Idle Registers (TIR) Function Select.
See Section 8 for details.
0=TIRs define in which channels to insert idle code
1=TIRs define in which channels to insert data from RSER (i.e., Per=Chan-
nel Loopback function)
ESR
CCR3.4
Elastic Stores Reset.
Setting this bit from a one to a zero will force the
elastic stores to a known depth. ESR is level triggered. Should be toggled
after RSYSCLK and TSYSCLK have been applied and are stable. Must be
set and cleared again for a subsequent reset. Do not leave this bit set high.
RSRE
CCR3.3
Receive Side Signaling Re–Insertion Enable.
See Section 7–2 for
details.
0=do not re–insert signaling bits into the data stream presented at the
RSER pin
1=re–insert the signaling bits into data stream presented at the RSER pin
THSE
CCR3.2
Transmit Side Hardware Signaling Insertion Enable.
See Section 7–2
for details.
0=do not insert signaling from the TSIG pin into the data stream presented
at the TSER pin
1=insert signaling from the TSIG pin into the data stream presented at the
TSER pin
TBCS
CCR3.1
Transmit Side Backplane Clock Select.
0=if TSYSCLK is 1.544 MHz
1=if TSYSCLK is 2.048 MHz
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