參數(shù)資料
型號: DS2154
廠商: Maxim Integrated Products, Inc.
英文描述: Enhanced E1 Single Chip Transceiver(改進(jìn)型E1單片收發(fā)器)
中文描述: 增強(qiáng)型E1單芯片收發(fā)器
文件頁數(shù): 32/71頁
文件大小: 654K
代理商: DS2154
DS2154
071498 32/71
5.2
CRC4 Count Register 1 (CRCCR1) is the most signifi-
cant word and CRCCR2 is the least significant word of a
10–bit counter that records word errors in the Cyclic
Redundancy Check 4 (CRC4). Since the maximum
CRC4 Error Counter
CRC4 count in a one second period is 1000, this counter
cannot saturate. The counter is disabled during loss of
sync at either the FAS or CRC4 level; it will continue to
count if loss of multiframe sync occurs at the CAS level.
CRCCR1: CRC4 COUNT REGISTER 1
(Address=02 Hex)
CRCCR2: CRC4 COUNT REGISTER 2
(Address=03 Hex)
(MSB)
(LSB)
(note 1)
(note 1)
(note 1)
(note 1)
(note 1)
(note 1)
CRC9
CRC8
CRC7
CRC6
CRC5
CRC4
CRC3
CRC2
CRC1
CRC0
SYMBOL
POSITION
NAME AND DESCRIPTION
CRC9
CRCCR1.1
MSB of the 10–bit CRC4 error count.
CRC0
CRCCR2.0
LSB of the 10–bit CRC4 error count.
NOTE:
1. The upper six bits of CRCCR1 at address 02 are the most significant bits of the 12–bit FAS error counter.
5.3
E–bit Count Register 1 (EBCR1) is the most significant
word and EBCR2 is the least significant word of a 10–bit
counter that records Far End Block Errors (FEBE) as
reported in the first bit of frames 13 and 15 on E1 lines
running with CRC4 multiframe. These count registers
E–Bit Counter
will increment once each time the received E–bit is set to
zero. Since the maximum E–bit count in a one second
period is 1000, this counter cannot saturate. The
counter is disabled during loss of sync at either the FAS
or CRC4 level; it will continue to count if loss of multi-
frame sync occurs at the CAS level.
EBCR1: E–BIT COUNT REGISTER 1
(Address=04 Hex)
EBCR2: E–BIT COUNT REGISTER 2
(Address=05 Hex)
(MSB)
(LSB)
(note 1)
(note 1)
(note 1)
(note 1)
(note 1)
(note 1)
EB9
EB8
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
SYMBOL
POSITION
NAME AND DESCRIPTION
EB9
EBCR1.1
MSB of the 10–bit E–Bit count.
EB0
EBCR2.0
LSB of the 10–bit E–Bit count.
NOTE:
The upper six bits of EBCR1 at address 04 are the least significant bits of the 12–bit FAS error counter.
CRCCR1
CRCCR2
EBCR1
EBCR2
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