- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385273 > DS2154 (Maxim Integrated Products, Inc.) Enhanced E1 Single Chip Transceiver(改進(jìn)型E1單片收發(fā)器) PDF資料下載
參數(shù)資料
| 型號： | DS2154 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Enhanced E1 Single Chip Transceiver(改進(jìn)型E1單片收發(fā)器) |
| 中文描述： | 增強(qiáng)型E1單芯片收發(fā)器 |
| 文件頁數(shù)： | 12/71頁 |
| 文件大?。?/td> | 654K |
| 代理商： | DS2154 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當(dāng)前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁
DS2154
071498 12/71
Receive Clock Input [RCLKI].
Clock used to clock
data through the receive side framer. This pin is nor-
mally tied to RCLKO. Can be internally connected to
RCLKO by tying the LIUC pin high. RCLKI must be
present for the parallel control port to operate properly.
PARALLEL CONTROL PORT PINS
Interrupt [INT].
Flags host controller during conditions
and change of conditions defined in the Status Regis-
ters 1 and 2. Active low, open drain output.
3–State Control [Test].
Set high to 3–state all output
and I/O pins (including the parallel control port). Set low
for normal operation. Useful in board level testing.
Bus Operation [MUX].
Set low to select non–multi-
plexed bus operation. Set high to select multiplexed bus
operation.
Data Bus [D0 to D7] or Address/Data Bus [AD0 to
AD7].
In non–multiplexed bus operation (MUX=0),
serves as the data bus. In multiplexed bus operation
(MUX=1), serves as a 8–bit multiplexed address / data
bus.
Address Bus [A0 to A6].
In non–multiplexed bus
operation (MUX=0), serves as the address bus. In mul-
tiplexed bus operation (MUX=1), these pins are not
used and should be tied low.
Bus Type Select [BTS].
Strap high to select Motorola
bus timing; strap low to select Intel bus timing. This pin
controls the function of the RD\(DS), ALE(AS), and
WR\(R/W\) pins. If BTS=1, then these pins assume the
function listed in parenthesis ().
Read Input [RD] (Data Strobe [DS]).
RD and DS are
active low signals when MUX=11. DS is active high
when MUX = 0. See bus timing diagrams.
Chip Select [CS].
Must be low to read or write to the
device. CS is an active low signal.
A7 or Address Latch Enable [ALE] (Address Strobe
[AS]).
In non–multiplexed bus operation (MUX=0),
serves as the upper address bit. In multiplexed bus
operation (MUX=1), serves to demultiplex the bus on a
positive–going edge.
Write Input [WR] (Read/Write [R/W]).
WR is an active
low signal.
LINE INTERFACE PINS
Master Clock Input [MCLK].
2.048 MHz (
±
50 ppm)
clock source with TTL levels is applied at this pin. This
clock is used internally for both clock/data recovery and
for jitter attenuation. A quartz crystal of 2.048 MHz may
be applied across MCLK and XTALD instead of the TTL
level clock source.
Quartz Crystal Driver [XTALD].
A quartz crystal of
2.048 MHz may be applied across MCLK and XTALD
instead of a TTL level clock source at MCLK. Leave
open circuited if a TTL clock source is applied at MCLK.
Eight Times Clock [8XCLK]
. 16.384 MHz clock that is
frequency locked to the 2.048 MHz clock provided from
the clock/data recovery block (if the jitter attenuator is
enabled on the receive side) or from the TCLKI pin (if the
jitter attenuator is enabled on the transmit side). Can be
internally disabled via the TEST2 register if not needed.
Line Interface Connect [LIUC].
Tie low to separate the
line interface circuitry from the framer/formatter circuitry
and activate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/
RCLKI pins. Tie high to connect the the line interface cir-
cuitry to the framer/formatter circuitry and deactivate
the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins.
When LIUC is tied high, the TPOSI/TNEGI/TCLKI/
RPOSI/RNEGI/RCLKI pins should be tied low.
Receive Tip and Ring
[
RTIP and RRING].
Analog
inputs for clock recovery circuitry. These pins connect
via a 1:1 transformer to either the E1 line. See Section
12 for an example.
Transmit Tip and Ring [TTIP and TRING].
Analog line
driver outputs. These pins connect via a 1:1.15 or
1:1.36 step–up transformer to the E1 line. See Section
12 for an example.
SUPPLY PINS
Digital Positive Supply [DVDD].
5.0 volts
±
5%.
Should be tied to the RVDD and TVDD pins.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2164Q | G.726 ADPCM Processor(G.726自適應(yīng)音頻脈沖編碼處理器) |
| DS2175 | T1/CEPT Elastic Store(T1/CEPT 彈性存儲器) |
| DS2180A | T1 Transceiver(T1收發(fā)器) |
| DS2187 | Receive Line Interface(接收線接口) |
| DS2250T | Soft Microcontroller Module(軟件微控制器模塊) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2154DK | 功能描述:KIT DESIGN E1 DS2154 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 傳感器類型:CMOS 成像，彩色（RGB） 傳感范圍:WVGA 接口:I²C 靈敏度:60 fps 電源電壓:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相關(guān)產(chǎn)品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
| DS2154L | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Enhanced E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2154L+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Enhanced E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2154LA2 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2154LA2+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Enhanced E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。