參數(shù)資料
型號(hào)： CYP15G0402DXB
廠商： Cypress Semiconductor Corp.
英文描述： Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器)
中文描述： 二，四的HOTLink SERDES的（四的HOTLink二并行轉(zhuǎn)換器）
文件頁(yè)數(shù)： 9/29頁(yè)
文件大?。?/td> 634K
代理商： CYP15G0402DXB
CYP15G0402DXB
CYV15G0402DXB
Document #: 38-02057 Rev. *G
Page 9 of 29
FRAMCHAR
Three-level Select
[5]
Static Control Input
Framing Character Select
. Used to control the type of character used for framing the
received data streams.
When MID, the framer looks for both positive and negative disparity versions of the
eight-bit Comma character.
When HIGH, the framer looks for both positive and negative disparity versions of the
K28.5 character.
Configuring FRAMCHAR to LOW is reserved for component test.
LVTTL Output Clock
Receive Character Clock Output
. These true and complement clocks are the Receive
interface clocks which are used to control timing of data output transfers. These clocks
are output continuously at either the dual-character rate (1/20
th
the serial bit-rate) or
character rate (1/10
th
the serial bit-rate) of the data being received, as selected by
RXRATE.
Three-level Select
[5]
Static Control Input
character boundaries (based on detection of one or more framing characters in the
received serial bit stream). This signal operates in conjunction with the type of framing
character selected.
RXCLKA±
RXCLKB±
RXCLKC±
RXCLKD±
RFMODE
Reframe Mode Select
. Used to control the type of character framing used to adjust the
When LOW, the Low-Latency Framer is selected. This will frame on each occurrence
of the selected framing character(s) in the received data stream. This mode of framing
stretches the recovered character clock for one or multiple cycles to align that clock with
the recovered data.
When MID, the Cypress-mode Multi-Byte parallel Framer is selected. This requires a
pair of the selected framing character(s), on identical 10-bit boundaries, within a span
of 50 bits, before the character boundaries are adjusted. The recovered character clock
remains in the same phase regardless of character offset.
When HIGH, the alternate mode Multi-Byte parallel Framer is selected. This requires
detection of the selected framing character(s) of the allowed disparities in the received
serial bit stream, on identical 10-bit boundaries, on four directly adjacent characters.
The recovered character clock remains in the same phase regardless of character
offset.
Device Control Signals
PARCTL
Three-level Select
[5]
,
Static Control Input
Parity Check/Generate Control
. Used to control the different parity check and
generate functions.
When LOW, parity checking is disabled, and the RXOPx outputs are all disabled
(High-Z).
When MID, theTXDx[9:0] inputs are checked (along with TXOPx) for valid ODD parity,
and ODD parity is generated for the RXDx[9:0] outputs and presented on RXOPx.
When HIGH, parity checking and generation are enabled. The TXDx[9:0] inputs are
checked (along with TXOPx) for valid ODD parity, and ODD parity is generated for the
RXDx[9:0] and COMDETx outputs and presented on RXOPx. See
Table 8
for details.
Reference Clock
. This clock input is used as the timing reference for the transmit PLL.
It is also used as the centering frequency of the Range Controller block of the Receive
CDR PLLs. This input clock may also be selected to clock the transmit input interface.
When driven by a a single-ended LVCMOS or LVTTL clock source, connect the clock
source to either the true or complement REFCLK input and leave the alternate REFCLK
input open (floating). When driven by an LVPECL clock source, the clock must be a
differential clock, using both inputs.
REFCLK±
Differential LVPECL
or single-ended
LVCMOS input clock
When TXCKSEL = LOW, REFCLK is also used as the clock for the parallel transmit data
(input) interface.
Serial Rate Select
. This input specifies the operating bit-rate range of both transmit and
receive PLLs. LOW = 195–400 MBaud, MID = 400–800 MBaud, HIGH =
800–1500 MBaud. When SPDSEL is LOW, setting TXRATE = HIGH (Half-rate
Reference Clock) is invalid.
SPDSEL
Three-level Select
[5]
,
Static Control Input
Pin Descriptions
CYP(V)15G0402DXB Quad HOTLink II SERDES (continued)
Name
I/O Characteristics Signal Description
相關(guān)PDF資料
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參數(shù)描述
CYP15G0402DXB-BGC 功能描述:電信線路管理 IC Quad Channel SERDES COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
CYP15G0402DXB-BGI 制造商:Cypress Semiconductor 功能描述:
CYP15G0402DXB-BGXC 功能描述:電信線路管理 IC Quad Ch HOTLink II GbE 1XFC SERDES RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
CYP15G0402DXB-BGXI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II⑩ SERDES
CYP15G0402DX-BGC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLinkII SERDES
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