- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380224 > CYP15G0402DXB (Cypress Semiconductor Corp.) Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器) PDF資料下載
參數(shù)資料
| 型號(hào)： | CYP15G0402DXB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器) |
| 中文描述： | 二，四的HOTLink SERDES的（四的HOTLink二并行轉(zhuǎn)換器） |
| 文件頁數(shù)： | 10/29頁 |
| 文件大?。?/td> | 634K |
| 代理商： | CYP15G0402DXB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁
CYP15G0402DXB
CYV15G0402DXB
Document #: 38-02057 Rev. *G
Page 10 of 29
Analog I/O and Control
OUTA±
OUTB±
OUTC±
OUTD±
INA±
INB±
INC±
IND±
OELE
CML Differential
Output
Differential Serial Data Outputs. These
PECL-compatible CML outputs (+3.3V refer-
enced) are capable of driving terminated transmission lines or standard fiber-optic trans-
mitter modules.
LVPECL Differential
Input
Differential Serial Data Inputs
. These inputs accept the serial data stream for deseri-
alization. The INx
±
serial streams are passed to the receiver Clock and Data Recovery
(CDR) circuits to extract the data content when INSELx = HIGH.
LVTTL Input,
asynchronous,
internal pull-up
Serial Driver Output Enable Latch Enable
. When OELE = HIGH, the signals on the
BOE[7:0] inputs directly control the OUTx± differential drivers.
When the BOE[x] input is HIGH, the associated OUTx± differential driver is enabled.
When the BOE[x] input is LOW, the associated OUTx± differential driver is powered
down.
When OELE returns LOW, the last values present on BOE[7:0] are captured in the
internal Output enable Latch.
The specific mapping of BOE[7:0] signals to transmit output enables is listed in
Table 2
.
If the device is reset (TRSTZ is sampled LOW), the latch is reset to disable all outputs.
Transmit and Receive BIST Latch Enable
. Active HIGH. When BISTLE = HIGH, the
signals on the BOE[7:0] inputs directly control the transmit and receive BIST enables.
BISTLE
LVTTL Input,
asynchronous,
internal pull-up
When the BOE[x] input is LOW, the associated transmit or receive channel is configured
to generate or compare the BIST sequence.
When the BOE[x] input is HIGH, the associated transmit or receive channel is configured
for normal data transmission or reception.
When BISTLE returns LOW the last values present on BOE[7:0] are captured in the
internal BIST Enable Latch.
The specific mapping of BOE[7:0] signals to transmit and receive BIST enables is listed
in
Table 2
.
When the latch is closed, if the device is reset (TRSTZ is sampled LOW), the latch is
reset to disable BIST on all transmit and receive channels.
Receive Channel Power-Control Latch Enable
. When RXLE = HIGH, the signals on
the BOE[7:0] directly control the power enables for the receive PLLs and analog logic.
RXLE
LVTTL Input,
asynchronous,
internal pull-up
When the BOE[7:0] input is HIGH, the receive channels PLL’s and analog logic are
active.
When the BOE[7:0] input is LOW, the receive channels are in a power-down mode.
When RXLE returns LOW, the last values present on BOE[7:0] are captured in the
internal RX PLL Enable Latch.
The specific mapping of BOE[7:0] signals to the associated receive channel enables is
listed in
Table 2
.
When the device is reset (TRSTZ = LOW), the latch is reset to disable all receive
channels.
BIST, Serial Output, and Receive Channel Enables
.
BOE[7:0]
LVTTL Input,
asynchronous,
internal pull-up
These inputs are passed to and through the Output Enable Latch when OELE is HIGH,
and captured in this latch when OELE returns LOW.
These inputs are passed to and through the BIST Enable Latch when BISTLE is HIGH,
and captured in this latch when BISTLE returns LOW.
These inputs are passed to and through the Receive Channel Enable Latch when RXLE
is HIGH, and captured in this latch when RXLE returns LOW.
Pin Descriptions
CYP(V)15G0402DXB Quad HOTLink II SERDES (continued)
Name
I/O Characteristics Signal Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYV15G0402DXB | Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器) |
| CYP15G0403DXB | Independent Clock Quad HOTLink II Transceiver(獨(dú)立時(shí)鐘，四熱連接II收發(fā)器) |
| CYV15G0403DXB | Independent Clock Quad HOTLink II Transceiver(獨(dú)立時(shí)鐘，四熱連接II收發(fā)器) |
| CYW15G0403DXB | Independent Clock Quad HOTLink II Transceiver(獨(dú)立時(shí)鐘，四熱連接II收發(fā)器) |
| CYRF69103 | Programmable Radio on Chip Low Power |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0402DXB-BGC | 功能描述:電信線路管理 IC Quad Channel SERDES COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0402DXB-BGI | 制造商:Cypress Semiconductor 功能描述: |
| CYP15G0402DXB-BGXC | 功能描述:電信線路管理 IC Quad Ch HOTLink II GbE 1XFC SERDES RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0402DXB-BGXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II⑩ SERDES |
| CYP15G0402DX-BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLinkII SERDES |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。