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參數(shù)資料
| 型號： | CYP15G0402DXB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器) |
| 中文描述： | 二，四的HOTLink SERDES的（四的HOTLink二并行轉(zhuǎn)換器） |
| 文件頁數(shù)： | 15/29頁 |
| 文件大小： | 634K |
| 代理商： | CYP15G0402DXB |
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CYP15G0402DXB
CYV15G0402DXB
Document #: 38-02057 Rev. *G
Page 15 of 29
In case no data is present at the input, this switching behavior
may result in brief RXCLKx frequency excursions from
REFCLK. However, the validity of the input data stream is
indicated by the LFIx output. The frequency of REFCLK is
required to be within ±1500ppm
[8]
of the frequency of the clock
that drives the REFCLK input of the remote transmitter to
ensure a lock to the incoming data stream.
Deserializer/Framer
Each CDR circuit extracts bits from the associated serial data
stream and clocks these bits into the Shifter/Framer at the
bit-clock rate. When enabled, the Framer examines the data
stream, looking for one or more Comma or K28.5 characters
at all possible bit positions. The location of this character in the
data stream is used to determine the character boundaries of
all following characters.
Framing Character
The CYP(V)15G0402DXB allows selection of one of two
combinations of framing characters to support requirements of
different interfaces. The selection of the framing character is
made through the FRAMCHAR input.
Table 5. Framing Character Selector
The specific bit combinations of these framing characters are
listed in
Table 5
. When the specific bit combination of the
selected framing character is detected by the Framer, the
boundaries of the characters present in the received data
stream are known.
Framer
The Framer on each channel operates in one of three different
modes, as selected by the RFMODE input. In addition, the
Framer for each channel may be enabled or disabled through
the RFENx input. When RFENx = LOW, the framer in that
receive path is disabled, and no combination of bits in a
received data stream will alter the character boundaries. When
RFENx = HIGH, the Framer selected by RFMODE is enabled
for that channel.
When RFMODE = LOW, the Low-Latency Framer is selected.
This Framer operates by stretching the recovered character
clock until it aligns with the received character boundaries. In
this mode, the Framer starts its alignment process on the first
detection of the selected framing character. To reduce the
impact on external circuits that make use of a recovered clock,
the clock period is not stretched by more than two bit-periods
in any one clock cycle. When operated with a character-rate
Notes:
11.
The standard definition of a Comma contains only seven bits. However, since all valid Comma characters within the 8B/10B character set also have the eighth
bit as an inversion of the seventh bit, the compare pattern is extended to a full eight bits to reduce the possibility of a framing error.
12. When Receive BIST is enabled on a channel, the Low-Latency Framer must not be enabled. The BIST sequence contains an aliased K28.5 framing character,
which causes the Receiver to update its character boundaries incorrectly.
output clock (RXRATE = LOW), the output of properly framed
characters may be delayed by up to nine character-clock
cycles from the detection of the selected framing character.
When operated with a half-character-rate output clock
(RXRATE = HIGH), the output of properly framed characters
may be delayed by up to 14 character-clock cycles from the
detection of the selected framing character.
[8]
When RFMODE is MID (open), the Cypress-mode Multi-Byte
Framer is selected. The required detection of multiple framing
characters makes the associated link much more robust to
incorrect framing due to aliased framing characters in the data
stream. In this mode, the Framer does not adjust the character
clock boundary, but instead aligns the character to the already
recovered character clock. This ensures that the recovered
clock will not contain any significant phase changes or hops
during normal operation or framing, and allows the recovered
clock to be replicated and distributed to other external circuits
or components using PLL-based clock distribution elements.
In this framing mode, the character boundaries are only
adjusted if the selected framing character is detected at least
twice within a span of 50 bits, with both instances on identical
10-bit character boundaries.
When RFMODE = HIGH, the Alternate-mode Multi-Byte
Framer is enabled. Like the Cypress-mode Multi-Byte Framer,
multiple framing characters must be detected before the
character boundary is adjusted. In this mode, the Framer does
not adjust the character clock boundary, but instead aligns the
character to the already recovered character clock. In this
mode, the data stream must contain a minimum of four of the
selected framing characters, received as consecutive
characters, on identical 10-bit boundaries, before character
framing is adjusted.
Framing is enabled for a channel when the associated RFENx
input is HIGH. When RFENx is LOW, the framer for the
associated channel is disabled. When a framer is disabled, no
changes are made to the recovered character boundaries on
that channel, regardless of the presence of framing characters
in the data stream.
Receive BIST Operation
The Receiver interfaces contain internal pattern generators
that can be used to validate both device and link operation.
These generators are enabled by the associated BOE[x]
signals listed in
Table 2
(when the BISTLE latch enable input
is HIGH). When enabled, a register in the associated receive
channel becomes a pattern generator and checker by logically
converting to a Linear Feedback Shift Register (LFSR). This
LFSR generates a 511-character sequence that includes all
Data and Special Character codes, including the explicit
violation symbols. This provides a predictable yet
pseudo-random sequence that can be matched to an identical
LFSR in the attached Transmitter(s). When synchronized with
the received data stream, the associated Receiver compares
each received character with each character generated by the
LFSR and indicates compare errors and BIST status at the
COMDETx and RXDx[1:0] bits of the Output Register
[12]
.
FRAMCHAR
LOW
Bits Detected in Framer
Character Name
Reserved for test
Bits Detected
MID (Open)
Comma+
or Comma-
+K28.5
or -K28.5
00111110XX
[11]
or
11000001XX
0011111010 or
1100000101
HIGH
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相關(guān)代理商/技術(shù)參數(shù) |
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| CYP15G0402DXB-BGC | 功能描述:電信線路管理 IC Quad Channel SERDES COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0402DXB-BGI | 制造商:Cypress Semiconductor 功能描述: |
| CYP15G0402DXB-BGXC | 功能描述:電信線路管理 IC Quad Ch HOTLink II GbE 1XFC SERDES RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0402DXB-BGXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II⑩ SERDES |
| CYP15G0402DX-BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLinkII SERDES |
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