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參數(shù)資料
| 型號(hào)： | CYP15G0402DXB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器) |
| 中文描述： | 二，四的HOTLink SERDES的（四的HOTLink二并行轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 23/29頁(yè) |
| 文件大?。?/td> | 634K |
| 代理商： | CYP15G0402DXB |
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CYP15G0402DXB
CYV15G0402DXB
Document #: 38-02057 Rev. *G
Page 23 of 29
t
REFD [29]
t
REFR [25, 26, 27]
t
REFF [25, 26, 27]
t
TREFDS
t
TREFDH
t
REFRX
[8]
REFCLK Duty Cycle
REFCLK Rise Time (20% – 80%)
REFCLK Fall Time (20% – 80%)
Transmit Data Setup Time to
REFCLK (TXCKSEL
=
LOW)
Transmit Data Hold Time from REFCLK
(TXCKSEL
=
LOW)
REFCLK Frequency Referenced to Received Clock Period
30
70
2
2
%
ns
ns
ns
ns
ppm
1.7
0.8
-1500
+1500
CYP(V)15G0402DXB Transmit Serial Outputs and TX PLL Characteristics
Over the Operating Range
Parameter
Description
Condition
Min.
5100
50
100
180
50
100
180
Max.
660
270
500
1000
270
500
1000
25
11
200
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
us
t
B
t
RISE [25]
Bit Time
CML Output Rise Time 20% – 80% (CML Test
Load)
SPDSEL = HIGH
SPDSEL = MID
SPDSEL = LOW
t
FALL [25]
CML Output Fall Time 80% – 20% (CML Test Load) SPDSEL = HIGH
SPDSEL = MID
SPDSEL = LOW
IEEE 802.3z
IEEE 802.3z
t
DJ [25, 30, 32]
t
RJ
[25, 31, 32]
t
TXLOCK
Deterministic Jitter (peak-peak)
Random Jitter (
σ
)
Transmit PLL lock to REFCLK
CYP(V)15G0402DXB Receive Serial Inputs and CDR PLL Characteristics
Over the Operating Range
t
RXLOCK
Receive PLL lock to input data stream (cold start)
Receive PLL lock to input data stream
376K
376K
46
UI
[33]
UI
UI
ps
ps
t
RXUNLOCK
t
JTOL
t
DJTOL
Receive PLL Unlock Rate
Total Jitter Tolerance
Deterministic Jitter Tolerance
IEEE 802.3z
IEEE 802.3z
600
370
Capacitance
[25]
Parameter
C
INTTL
C
INPECL
Notes:
29. The duty cycle specification is a simultaneous condition with the t
REFH
and t
REFL
parameters. This means that at faster character rates the REFCLK duty cycle
cannot be as large as 30% – 70%.
30. While sending continuous K28.5s, outputs loaded to a balanced 100
load, measured at the cross point of differential outputs, over the operating range.
31. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLK input, over the operating
range.
32. Total jitter is calculated at an assumed BER of 1E
12. Hence: total jitter (t
) = (t
RJ
* 14) + t
.
33. Receiver UI (Unit Interval) is calculated as 1/(f
*20) (when RXRATE = HIGH) or 1/(f
* 10) (when RXRATE = LOW) if no data is being received, or 1 / (f
* 20)
(when RXRATE = HIGH) or 1/(f
REF
* 10) (when RXRATE = LOW) of the remote transmitter if data is being received. In an operating link this is equivalent to t
B
.
Description
Test Conditions
Max.
7
4
Unit
pF
pF
TTL Input Capacitance
PECL input Capacitance
T
A
= 25°C, f
0
= 1 MHz, V
CC
= 3.3V
T
A
= 25°C, f
0
= 1 MHz, V
CC
= 3.3V
CYP(V)15G0402DXB REFCLK Switching Characteristics
Over the Operating Range (continued)
Parameter
Description
Min.
Max.
Unit
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相關(guān)代理商/技術(shù)參數(shù) |
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| CYP15G0402DXB-BGC | 功能描述:電信線路管理 IC Quad Channel SERDES COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0402DXB-BGI | 制造商:Cypress Semiconductor 功能描述: |
| CYP15G0402DXB-BGXC | 功能描述:電信線路管理 IC Quad Ch HOTLink II GbE 1XFC SERDES RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0402DXB-BGXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II⑩ SERDES |
| CYP15G0402DX-BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLinkII SERDES |
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