參數(shù)資料
型號(hào)： CYP15G0402DXB
廠(chǎng)商： Cypress Semiconductor Corp.
英文描述： Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器)
中文描述： 二，四的HOTLink SERDES的（四的HOTLink二并行轉(zhuǎn)換器）
文件頁(yè)數(shù)： 16/29頁(yè)
文件大小： 634K
代理商： CYP15G0402DXB
CYP15G0402DXB
CYV15G0402DXB
Document #: 38-02057 Rev. *G
Page 16 of 29
When the BISTLE signal is HIGH, any BOE[x] input that is
LOW enables the BIST generator/checker in the associated
Receive channel (or the BIST generator in the associated
Transmit channel). When BISTLE returns LOW, the values of
all BOE[x] signals are captured in the BIST Enable Latch.
These values remain in the BIST Enable Latch until BISTLE is
returned HIGH. All captured signals in the BIST Enable Latch
are set HIGH (i.e., BIST is disabled) following a device reset
(TRSTZ is switched LOW).
When BIST is first recognized as being enabled in the
Receiver, the LFSR is preset to the BIST-loop start-code of
D0.0. This code D0.0 is sent only once per BIST loop. The
status of the BIST progress and any character mismatches is
presented on the COMDETx and RXDx[1:0] status outputs.
COMDETx, RXDx[1:0] indicates 010b or 100b for one character
period per BIST loop to indicate loop completion. This status can be
used to check test pattern progress. The status reported by the
BIST state machine on COMDETX and RXDx[1:0] are listed in
Table 6
.
The specific patterns checked by each receiver are described
in detail in the Cypress application note “HOTLink Built-In
Self-Test.”
The
sequence
CYP(V)15G0402DXB is identical to that in the CY7B933 and
CY7C924DX, allowing interoperable systems to be built when
used at compatible serial signaling rates. If the number of
invalid characters received ever exceeds the number of valid
characters by 16, the receive BIST state machine aborts the
compare operations and resets the LFSR to the D0.0 state to
look for the start of the BIST sequence again.
The BIST state machine requires the characters to be correctly
framed for it to detect the BIST sequence. If the Low Latency
Framer is enabled (RFMODE = LOW), the Framer will misalign
to an aliased K28.5 framing character within the BIST
sequence. If the Alternate Multi-Byte Framer is enabled
(RFMODE = HIGH), it is necessary to frame the receiver
before BIST is enabled.
compared
by
the
Power Control
The CYP(V)15G0402DXB supports user control of the
powered up or down state of each transmit and receive
channel. The receive channels are controlled by the RXLE
signal and the values present on the BOE[7:0] bus. The
transmit channels are controlled by the OELE signal and the
values present on the BOE[7:0] bus. Powering down unused
channels will save power and reduce system heat generation.
Controlling system power dissipation will improve the system
performance.
Receive Channels
When RXLE is HIGH, the signals on the BOE[7:0] inputs
directly control the power enables for the receive PLLs and
analog circuits. When a BOE[7:0] input is HIGH, the
associated receive channel [A through D] PLL and analog
logic are active. When a BOE[7:0] input is LOW, the
associated receive channel [A through D] PLL and analog
circuits are powered down. When RXLE returns LOW, the last
values present on the BOE[7:0] inputs are captured. The
specific BOE[7:0] input signal associated with a receive
channel is listed in
Table 2
.
Any disabled receive channel will indicate a constant LFIx
output.
When a disabled receive channel is re-enabled, the status of
the associated LFIx output and data on the parallel outputs for
the associated channel may be indeterminate for up to 2 ms.
Transmit Channels
When OELE is HIGH, the signals on the BOE[7:0] inputs
directly control the power enables for the Serial Drivers. When
a BOE[x] input is HIGH, the associated Serial Driver is
enabled. When a BOE[x] input is LOW, the associated Serial
Driver is disabled and powered down. If the Serial Driver of a
channel is disabled, the internal logic for that channel is
powered down. When OELE returns LOW, the values present
on the BOE[7:0] inputs are latched in the Output Enable Latch.
Device Reset State
When the CYP(V)15G0402DXB is reset by assertion of
TRSTZ, the Transmit Enable and Receive Enable Latches are
both cleared, and the BIST Enable Latch is preset. In this
state, all transmit and receive channels are disabled, and BIST
is disabled on all channels.
Following a device reset, it is necessary to enable the transmit
and receive channels used for normal operation. This can be
done by sequencing the appropriate values on the BOE[7:0]
inputs while the OELE and RXLE signals are raised and
lowered. For systems that do not require dynamic control of
power, or want the part to power up in a fixed configuration, it
is also possible to strap the RXLE and OELE control signals
HIGH to permanently enable their associated latches.
Connection of the associated BOE[7:0] signals to a stable
HIGH will then enable the respective transmit and receive
channels as soon as the TRSTZ signal is deasserted.
Table 6. BIST Status Bits
Status
P
Description
C
0
R
R
BIST Mode
7
BIST Data Compare
. Data Character
compared correctly.
7
BIST Command Compare
. Command
Character compared correctly.
2
BIST Last Good
. Last Character of BIST
sequence detected and valid.
5 Reserved
4
BIST Last Bad
. Last Character of BIST
sequence was detected invalid.
1
BIST Start
. RXBISTEN recognized on this
channel, but character compares have not
yet commenced. Also presented when the
receive PLL is tracking REFCLK instead of
the selected data stream.
6
BIST Error
. While comparing characters, a
mismatch was found in one or more of the
decoded character bits.
3
BIST Wait
. The receiver is comparing
characters. but has not yet found the start of
BIST character to enable the LFSR.
0
0
0
0
1
0
1
0
0
1
1
0
1
0
1
0
1
1
1
0
1
1
1
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CYP15G0402DX-BGC 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Quad HOTLinkII SERDES
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