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參數(shù)資料
| 型號(hào)： | CYP15G0402DXB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器) |
| 中文描述： | 二，四的HOTLink SERDES的（四的HOTLink二并行轉(zhuǎn)換器） |
| 文件頁數(shù)： | 17/29頁 |
| 文件大?。?/td> | 634K |
| 代理商： | CYP15G0402DXB |
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CYP15G0402DXB
CYV15G0402DXB
Document #: 38-02057 Rev. *G
Page 17 of 29
Output Bus
Each receive channel presents a 12-signal output bus
consisting of:
a 10-bit data bus
a COMMA detect indicator
a parity bit.
The signals present on this output bus are shown in
Table 7
.
The framed 10-bit value is presented to the associated Output
Register, along with a status output (COMDETx) indicating if
the character in the output register matches the selected
framing characters.
The COMDETx output is HIGH when the character in the
Output Register of the associated channel contains the
selected framing character at the proper character boundary,
and LOW for all other bit combinations.
When the Low-Latency Framer and half-rate receive port
clocking are also enabled (RFMODE = LOW, RXRATE =
HIGH), the Framer will stretch the recovered clock to the
nearest 20-bit boundary such that the rising edge of RXCLKx+
occurs when COMDETx is present on the associated output
bus.
When the Cypress or Alternate Mode Framer is enabled and
half-rate receive port clocking are also enabled (RFMODE
≠
LOW and RXRATE = HIGH), the output clock is not modified
when framing is detected, but a single pipeline stage may be
added or subtracted from the data stream by the Framer logic
such that the rising edge of RXCLKx+ occurs when COMDETx
is present on the associated output bus.
This adjustment only occurs when the Framer is enabled
(RFEN = HIGH). When the Framer is disabled, the clock
boundaries are not adjusted, and COMDETx may be asserted
during the rising edge of RXCLK– (if an odd number of
characters were received following the initial framing).
Notes:
13. The RXOPx and COMDETx outputs are also driven from the associated output register, but their generation and interpretation are separate from the data bus.
14. Receive path parity output drivers are disabled when PARCTL is low
15. When BIST is not enabled,COMDETx is usually driven to a logic 0, but will be driven high when the character in the output buffer is the selected framing character.
Parity Generation
In addition to the 10-bit data and COMDETx status bit, an
RXOPx ODD parity output can also be generated for each
channel. Parity can be generated on
the RXDx[9:0] character
RXDx[9:0] character and COMDETx status bit.
These modes differ in the number of bits which are included in
the parity calculation. Only ODD parity is provided which
ensures that at least one bit of the data bus is always a logic-1.
Those bits covered by parity generation are listed in
Table 8
.
Parity generation is enabled through the three-level select
PARCTL input. When PARCTL = LOW, parity checking is
disabled, and the RXOPx outputs are all disabled (High-Z).
When PARCTL is MID, ODD parity is generated for the
RXDx[9:0] bits.
When PARCTL is HIGH, ODD parity is generated for both the
RXDx[9:0] bits and the associated COMDETx signal.
Table 8. Output Register Parity Generation
BIST Status State Machine
When a receive path is enabled to look for and compare the
received data stream with the BIST pattern, the COMDETx
and RXDx[1:0] bits identify the present state of the BIST
compare operation.
The BIST state machine has multiple states, as shown in
Figure 2
and
Table 6
. When the receive PLL detects an
out-of-lock condition, the BIST state is forced to the
Start-of-BIST state, regardless of the present state of the BIST
state machine. If the number of detected errors ever exceeds
the number of valid matches by greater than 16, the state
machine is forced to the WAIT_FOR_BIST state where it
monitors the interface for the first character (D0.0) of the next
BIST sequence. Also, if the Elasticity Buffer ever hits an
overflow/underflow condition, the status is forced to the
BIST_START until the buffer is re-centered (approximately
nine character periods).
Table 7. Output Register Bit Assignment
Signal Name
RXOPx
[13]
COMDETx
[13]
RXDx[0]
(LSB)
RXDx[1]
RXDx[2]
RXDx[3]
RXDx[4]
RXDx[5]
RXDx[6]
RXDx[7]
RXDx[8]
RXDx[9]
(MSB)
Bus Weight
10B Name
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
a
b
c
d
e
i
f
g
h
j
Signal Name
COMDETx
RXDx[0]
RXDx[1]
RXDx[2]
RXDx[3]
RXDx[4]
RXDx[5]
RXDx[6]
RXDx[7]
RXDx[8]
RXDx[9]
Receive Parity Generate Mode (PARCTL)
LOW
[14]
MID
HIGH
X
[15]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0402DXB-BGC | 功能描述:電信線路管理 IC Quad Channel SERDES COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0402DXB-BGI | 制造商:Cypress Semiconductor 功能描述: |
| CYP15G0402DXB-BGXC | 功能描述:電信線路管理 IC Quad Ch HOTLink II GbE 1XFC SERDES RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0402DXB-BGXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II⑩ SERDES |
| CYP15G0402DX-BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLinkII SERDES |
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