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參數(shù)資料
| 型號： | CYP15G0402DXB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器) |
| 中文描述： | 二，四的HOTLink SERDES的（四的HOTLink二并行轉(zhuǎn)換器） |
| 文件頁數(shù)： | 7/29頁 |
| 文件大?。?/td> | 634K |
| 代理商： | CYP15G0402DXB |
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CYP15G0402DXB
CYV15G0402DXB
Document #: 38-02057 Rev. *G
Page 7 of 29
Pin Descriptions
CYP(V)15G0402DXB Quad HOTLink II SERDES
Name
I/O Characteristics Signal Description
Transmit Path Data Signals
TXPERA
TXPERB
TXPERC
TXPERD
LVTTL1 Output,
changes relative to
REFCLK
↑
[
4
]
Transmit Path Parity Error
. Active HIGH. Asserted (HIGH) if parity checking is enabled
and a parity error is detected at the shifter. This output is HIGH for one transmit character
clock period to indicate detection of a parity error in the character presented to the
shifter.
If a parity error is detected, the character in error is replaced with the 10-bit character,
1001111000, to force a corresponding bad-character detection at the remote end of the
link. This replacement takes place only when parity checking is enabled (PARCTL
≠
LOW).
When BIST is enabled for the specific transmit channel, BIST progress is presented on
these outputs. Once every 511 character times, the associated TXPERx signal will pulse
HIGH for one transmit-character clock period to indicate a complete pass through the
BIST sequence.
These outputs also provide indication of a transmit Phase-Align Buffer underflow or
overflow. When the transmit Phase-Align Buffers are enabled (TXCKSEL
≠
LOW, or
TXCKSEL = LOW and TXRATE = HIGH), if an underflow or overflow condition is
detected, TXPERx for the channel in error is asserted and remains asserted until either
an atomic Word Sync Sequence is transmitted or TXRST is sampled LOW to re-center
the transmit Phase-Align Buffers.
Transmit Data Inputs
. These inputs are captured on the rising edge of the transmit
interface clock as selected by TXCKSEL and passed to the transmit shifter.
TXDA[9:0]
TXDB[9:0]
TXDC[9:0]
TXDD[9:0]
LVTTL Input,
synchronous,
sampled by the
respective TXCLKx
↑
or REFCLK
↑
[
4
]
LVTTL Input,
synchronous,
sampled by the
respective TXCLKx
↑
or REFCLK
↑
[
4
]
TXDx[9:0] specify the specific transmission character to be sent.
TXOPA
TXOPB
TXOPC
TXOPD
Transmit Path Odd Parity
. When parity checking is enabled (PARCTL
≠
LOW), the
ODD parity captured at these inputs is XORed with the bits on the associated TXDx bus
to verify the integrity of the captured character.
Transmit Path Clock and Control
TXCLKO±
LVTTL Output
Transmit Clock Output
. This true and complement clock is synthesized by the transmit
PLL and is synchronous to the internal transmit character clock. It has the same
frequency as REFCLK (when TXRATE = LOW), or twice the frequency of REFCLK
(when TXRATE = HIGH). This output clock has no direct phase relationship to REFCLK.
Transmit Clock Select
.
TXCKSEL
Three-level Select
[5]
Static Control Input
Selects the clock source used to write data into the transmit Input Register of the
transmit channel(s)
When LOW, all four input registers are clocked by REFCLK
↑
.
When TXCKSEL is MID, TXCLKx
↑
is used as the input register clock for the associated
TXDx[9:0] and TXOPx.
When HIGH, TXCLKA
↑
is used to clock data into the Input Register for all channels.
When TXCKSEL = MID or HIGH (TXCLKx or TXCLKA selected to clock input register),
TXRATE = HIGH (Half-rate REFCLK) is an invalid mode of operation.
Transmit Path Input Clocks
. These inputs are only used when TXCKSEL
≠
LOW.
TXCLKA
TXCLKB
TXCLKC
TXCLKD
LVTTL Clock Input
asynchronous,
internal pull-up
These clocks must be frequency-coherent to REFCLK, but may be offset in phase.
The internal operating phase of each input clock (relative to REFLCK or TXCLKO
±
) is
adjusted when TXRST = LOW and locked when TXRST = HIGH.
Notes:
4.
When REFCLK is configured for half-rate operation (TXRATE = HIGH), these inputs are sampled (or the outputs change) relative to both the rising and falling
edges of REFCLK
Three-level select inputs are used for static configuration. They are ternary (not binary) inputs that make use of non-standard logic levels of LOW, MID, and
HIGH. The LOW level is usually implemented by direct connection to V
(ground). The HIGH level is usually implemented by direct connection to V
CC
. When
not connected or allowed to float, a three-level select input will self-bias to the MID level.
5.
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相關(guān)代理商/技術(shù)參數(shù) |
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| CYP15G0402DXB-BGC | 功能描述:電信線路管理 IC Quad Channel SERDES COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0402DXB-BGI | 制造商:Cypress Semiconductor 功能描述: |
| CYP15G0402DXB-BGXC | 功能描述:電信線路管理 IC Quad Ch HOTLink II GbE 1XFC SERDES RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0402DXB-BGXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II⑩ SERDES |
| CYP15G0402DX-BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLinkII SERDES |
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