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參數(shù)資料
| 型號： | CYP15G0402DX-BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Quad HOTLinkII SERDES |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.52 MM HEIGHT, THERMALLY ENHANCED, BGA-256 |
| 文件頁數(shù)： | 9/27頁 |
| 文件大?。?/td> | 852K |
| 代理商： | CYP15G0402DX-BGI |
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CYP15G0402DX
PRELIMINARY
Document #: 38-02023 Rev. *B
Page 9 of 27
OELE
LVTTL Input,
asynchronous,
internal pull-up
Serial Driver Output Enable Latch Enable
. When OELE = HIGH, the signals on the
BOE[7:0] inputs directly control the OUTx
±
differential drivers. When the BOE[x] input
is HIGH, the associated OUTx
±
differential driver is enabled. When the BOE[x] input is
LOW, the associated OUTx
±
differential driver is powered down. When OELE returns
LOW, the last values BOE[7:0] are captured. The specific mapping of BOE[7:0] signals
to transmit output enables is listed in
Table 2
. If the device is reset, the latch is reset to
enable all outputs.
Transmit and Receive BIST Latch Enable
. When BISTLE = HIGH, the signals on the
BOE[7:0] inputs directly control the transmit and receive BIST enables. When BOE[x]
input is LOW, the associated transmit or receive channel is configured to generate or
compare the BIST sequence. When the BOE[x] input is HIGH, the associated transmit
or receive channel is configured for normal data mode. When BISTLE returns LOW,
value present on BOE[7:0] is captured. The specific mapping of BOE[7:0] signals to
transmit and receive BIST enables is listed in
Table 2
. If the device is reset, this enable
latch is reset to disable BIST on all transmit and receive channels.
Receive Channel Power-Control Latch Enable
. When RXLE = HIGH, the signals on
the BOE[7:0] directly control the power enables for the receive PLLs and analog logic.
When the BOE[7:0] input is HIGH, the all receive channels PLL
’
s and analog logic are
active. When the BOE[7:0] input is LOW, all the receive channels are in a power down
mode. When RXLE returns LOW, BOE[7:0] values are captured. The specific mapping
of BOE[7:0] signals to the associated receive channel enables is listed in
Table 2
. If the
device is reset, the latch is reset to enable all receive channels.
BIST, Serial Output, and Receive Channel Enables
. These inputs are passed through
the output enable latch when OELE is HIGH, and captured in this latch when OELE
returns LOW. These inputs are passed through the BIST enable latch when BISTLE is
HIGH, and captured in this latch when BISTLE returns LOW. These inputs are passed
through the Receive Channel enable latch when RXLE is HIGH, and captured in this
latch when RXLE returns LOW.
Link Fault Indication Output
. Active LOW. LFI* is the logical OR of three internal
conditions on the associated channel: 1. received serial data frequency outside
expected range; 2. analog amplitude below expected levels; and 3. transition density
lower than expected.
BISTLE
LVTTL Input,
asynchronous,
internal pull-up
RXLE
LVTTL Input,
asynchronous,
internal pull-up
BOE[7:0]
LVTTL Input,
asynchronous,
internal pull-up
LFIA
LFIB
LFIC
LFID
JTAG Interface
TMS
LVTTL Output,
changes following
RXCLKx
↑
LVCMOS Input,
internal pull-up
LVCMOS Input,
internal pull-down
Three-state
LVCMOS Output
LVCMOS Input,
internal pull-up
LVCMOS Input,
internal pull-up
Test Mode Select. Enables JTAG Test Mode
TCLK
JTAG Test Clock
TDO
Test Data Out
. JTAG data output buffer which is High-Z while JTAG test mode is not
selected.
Test Data In
. JTAG data input port.
TDI
TRSTZ
Test Reset
. JTAG and full chip reset. Active LOW. Initializes the JTAG controller and all
other state machines.
Power
V
CC
GND
+3.3V power
Signal and power ground for all internal circuits
Pin Descriptions
Quad HOTLink II SERDES
Name
I/O Characteristics
Signal Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYP15G0402DXB | Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器) |
| CYV15G0402DXB | Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器) |
| CYP15G0403DXB | Independent Clock Quad HOTLink II Transceiver(獨(dú)立時(shí)鐘，四熱連接II收發(fā)器) |
| CYV15G0403DXB | Independent Clock Quad HOTLink II Transceiver(獨(dú)立時(shí)鐘，四熱連接II收發(fā)器) |
| CYW15G0403DXB | Independent Clock Quad HOTLink II Transceiver(獨(dú)立時(shí)鐘，四熱連接II收發(fā)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0402DX-EVAL | 功能描述:界面開發(fā)工具 Quad Ch HOTLink II GbE 1XFC SERDES RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| CYP15G0403DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver Single 3.3V supply |
| CYP15G0403DXB_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Transceiver |
| CYP15G0403DXB_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver |
| CYP15G0403DXB_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver Single 3.3V supply |
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