參數(shù)資料
型號(hào)： CYP15G0402DX-BGI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Quad HOTLinkII SERDES
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, 1.52 MM HEIGHT, THERMALLY ENHANCED, BGA-256
文件頁(yè)數(shù)： 11/27頁(yè)
文件大?。?/td> 852K
代理商： CYP15G0402DX-BGI
CYP15G0402DX
PRELIMINARY
Document #: 38-02023 Rev. *B
Page 11 of 27
CYP15G0402DX HOTLink II SERDES Operation
The CYP15G0402DX is designed to support transfer of large
quantities of data, using high-speed serial links. This device
contains four byte wide channels.
CYP15G0402DX Transmit Data Path
Data Path
The transmit path of the CYP15G0402DX supports four
character-wide data paths. These four data paths are inter-
nally unencoded and require input data that is encoded for
reliable transport.
Input Register
The bits in the Input Register for each channel have fixed bit
assignments, as listed in
Table 1
.
Each input register captures 10 bits on each input clock cycle.
When parity checking is enabled, the TXOPx parity input is
also captured in the associated input register.
Input Register Clocking
The transmit Input Registers can be configured to accept data
relative to different clock sources. The selection of the clock
source is controlled by TXCKSEL.
When TXCKSEL is LOW, the transmit Input Registers capture
data synchronous to the TXCLKO a derivative of REFCLK.
When TXCKSEL is MID, the rising edge of TXCLK is used to
capture the data at the associated TXDx[9:0] and TXOPx
inputs. When TXCKSEL is HIGH, the rising edge of TXCLKA
is used to capture the data at the associated TXDx[9:0] and
TXOPx inputs on all four channels.
Phase-Align Buffer
Data from the Input Registers is normally routed to the
associated Phase-Align Buffer. If the transmit Input Registers
are configured to capture data synchronous to REFCLK
(TXCKSEL = LOW), the Phase-Align Buffers are bypassed
and data is passed directly to the parity check and serializer
blocks.
When the Input Registers are clocked with REFCLK and
TXCKSEL
≠
LOW, the Phase-Align Buffers are enabled. These
buffers will absorb clock phase differences between the
presently selected input clock and the internal character clock.
TXRST when low will Initialize the Phase-Align Buffers. When
TXRST is returned HIGH, the present input clock phase
relative to REFCLK is set.
Once set, the input clocks are allowed to skew in time up to
half a character period in either direction relative to REFCLK.
This time-shift allows the delay paths of the character clocks
to change due to operating voltage and temperature, while not
affecting operation.
Parity Support
In addition to the ten data and control bits that are captured at
each channel, a TXOPx input is also available on each
channel. This allows the CYP15G0402DX to support ODD
parity checking for each channel. When PARCTL is LOW,
parity checking is disabled. When PARCTL is MID or HIGH,
parity is checked on the TXDx[9:0] and TXOPx bits.
If parity checking is enabled (PARCTL
≠
LOW) and a parity
error is detected, the 10-bit character in error is replaced with
the 1001111000 pattern an invalid character.
Transmit BIST
The transmitter interfaces contains an internal BIST pattern
generators that can be used to validate both device and link
operation. This generator is enabled by the associated BOE[x]
signals listed in
Table 2
and when BISTLE latch enable input
is HIGH. When enabled, a register in the associated transmit
channel becomes a pattern generator. This 511-character
sequence that includes all Data and Special Character codes,
including the explicit violation symbols. This provides a
predictable yet pseudo-random sequence that can be
matched to an identical receiver.
When the BISTLE signal is HIGH, any BOE[x] input that is
LOW enables the BIST generator in that associated transmit
channel or the BIST checker in the associated receive
channel. When BISTLE returns LOW, the values of all BOE[x]
signals are captured in the BIST Enable Latch. BIST is
disabled following a device reset by TRSTZ.
All data and data-control information present at the associated
TXDx[7:0] and TXCTx[1:0] inputs are ignored when BIST is
active on that channel. If the receive channels are configured
for common clock operation (RXCKSEL
≠
MID) each pass is
preceded by a 16-character Word Sync Sequence to allow
Elasticity Buffer alignment and reset of clock phase.
Table 1. Input Register Bit Mapping
Signal Name
TXDx[0]
(LSB)
TXDx[1]
TXDx[2]
TXDx[3]
TXDx[4]
TXDx[5]
TXDx[6]
TXDx[7]
TXDx[8]
TXDx[9]
(MSB)
TXOPx
[3]
Bus Weight
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
10B Name
a
[2]
b
c
d
e
i
f
g
h
j
Notes:
2.
3.
LSB is shifted out first.
The TXOPx inputs are also captured in the associated input register, but their interpretation is under the separate control of PARCTL.
相關(guān)PDF資料
PDF描述
CYP15G0402DXB Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器)
CYV15G0402DXB Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器)
CYP15G0403DXB Independent Clock Quad HOTLink II Transceiver(獨(dú)立時(shí)鐘，四熱連接II收發(fā)器)
CYV15G0403DXB Independent Clock Quad HOTLink II Transceiver(獨(dú)立時(shí)鐘，四熱連接II收發(fā)器)
CYW15G0403DXB Independent Clock Quad HOTLink II Transceiver(獨(dú)立時(shí)鐘，四熱連接II收發(fā)器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CYP15G0402DX-EVAL 功能描述:界面開(kāi)發(fā)工具 Quad Ch HOTLink II GbE 1XFC SERDES RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類(lèi)型:RS-485 工具用于評(píng)估:ADM3485E 接口類(lèi)型:RS-485 工作電源電壓:3.3 V
CYP15G0403DXB 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver Single 3.3V supply
CYP15G0403DXB_07 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Transceiver
CYP15G0403DXB_09 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver
CYP15G0403DXB_11 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver Single 3.3V supply
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*