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參數(shù)資料
| 型號： | CYP15G0402DX-BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Quad HOTLinkII SERDES |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.52 MM HEIGHT, THERMALLY ENHANCED, BGA-256 |
| 文件頁數(shù)： | 10/27頁 |
| 文件大?。?/td> | 852K |
| 代理商： | CYP15G0402DX-BGI |
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CYP15G0402DX
PRELIMINARY
Document #: 38-02023 Rev. *B
Page 10 of 27
Name
I/O Characteristics
3-Level Select
[1]
Static Control Input
Signal Description
FRAMCHAR
Framing Character Select. Used to control the type of character used for framing the
received data streams. When LOW, the framer looks for an 8-bit positive COMMA
character in the data stream. When MID, the framer looks for both positive and negative
disparity versions of the 8-bit COMMA character. When HIGH, the framer looks for both
positive and negative disparity versions of the K28.5 character.
Reframe Mode Select. Used to control the type of character framing system. This
signal operates in conjunction with the presently enabled channel bonding mode, and
the type of framing character selected. When LOW, the low-latency framer is selected.
This will frame on the first occurrence of the selected framing character in the received
data stream. This framing mode stretches the recovered clock for multiple cycles to
align that clock with the recovered data. When MID, the Cypress-mode multi-byte
parallel framer is selected. This requires a pair of the selected framing character, on
identical 10-bit boundaries, within a span of 50 bits, before the character boundaries
are adjusted. The recovered character clock remains in the same phasing regardless
of character offset. When HIGH, the alternate mode multi-byte parallel framer is
selected. This requires detection of the selected framing character of the allowed
disparities in the received data stream, on identical 10-bit boundaries, on four directly
adjacent characters. The recovered character clock remains in the same phasing
regardless of character offset.
RFMODE
3-Level Select
[1]
Static Control Input
Receive Path Clock and Clock Control
RXCLKA
±
RXCLKB
±
RXCLKC
±
RXCLKD
±
RFENA
RFENB
RFENC
RFEND
RXCKSEL
3-Level Select
[1]
Static Control Input
Three-state, LVTTL
Output clock
Static control input
Receive Character Clock
. These true and complement clocks are the Receive
interface clocks which are used to control timing of data output transfers. These clocks
are output continuously at either character rate of 1/20th or 1/10th the serial bit-rate of
the input data.
Reframe Enable
. Active HIGH. When HIGH the framer for the associated channel is
enabled to frame as per the framing mode and selected framing character.
LVTTL Input,
asynchronous,
internal pull-down
Receive Clock Mode
. Selects the receive clock-source used to transfer data to the
output registers. When LOW, all four output registers are clocked by REFCLK.
RXCLKB
±
and RXCLKD
±
outputs are disabled (High-Z), and RXCLKA
±
and
RXCLKC
±
present buffered and delayed forms of REFCLK. This clocking mode is
required for channel bonding across multiple devices. When MID, each RXCLKx
±
output follows the recovered clock for the respective channel, as selected by RXRATE.
When HIGH, and channel bonding is enabled in dual-channel mode (RX modes 3 and
5), RXCLKA
±
outputs the recovered clock from either receive channel A or receive
channel B as selected by RXCLKB+, and RXCLKC
±
outputs the recovered clock from
either receive channel C or receive channel D as selected by RXCLKD+. These output
clocks may operate at the character-rate or half the character-rate as selected by
RXRATE. When HIGH and channel bonding is enabled in quad channel mode (RX
modes 6 and 8), or if the receive channels are operated in independent mode (RX
modes 0 and 2), RXCLKA
±
and RXCLKC
±
output the recovered clock from receive
channel A, B, C, or D, as selected by RXCLKB+ and RXCLKD+. This output clock may
operate at the character-rate or half the character-rate as selected by RXRATE.
Device Control Signals
PARCTL
3-Level Select
[1]
,
Static Control Input
Parity Check/Generate Control
. Used to control the different parity checks. When
LOW, parity checking and generation are disabled, and the RXOPx output drivers are
disabled. When MID, the TXDx[9:0] inputs are checked, along with TXOPx, for valid
ODD parity, and valid ODD parity is generated for the RXDx[9:0] outputs and presented
on RXOPx. When HIGH, the TXDx[9:0] inputs are checked, along with TXOPx, for valid
ODD parity. Valid ODD parity is generated for the RXDx[9:0] and COMDETx outputs
and presented on RXOPx.
Note:
1.
3-Level select inputs are used for static configuration. They are ternary (not binary) inputs that make use of non-standard logic levels of LOW, MID, and HIGH.
The LOW level is usually implemented by direct connection to V
(ground). The HIGH level is usually implemented by direct connection to V
CC
(power). When
not connected or allowed to float, a 3-Level select input will self-bias to the MID level.
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