參數(shù)資料
型號(hào)： CYP15G0402DX-BGI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Quad HOTLinkII SERDES
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, 1.52 MM HEIGHT, THERMALLY ENHANCED, BGA-256
文件頁(yè)數(shù)： 19/27頁(yè)
文件大?。?/td> 852K
代理商： CYP15G0402DX-BGI
CYP15G0402DX
PRELIMINARY
Document #: 38-02023 Rev. *B
Page 19 of 27
CYP15G0402DX Transmit Serial Outputs and TX PLL Characteristics
Over the Operating Range
Parameter
t
B
t
RISE
Description
Condition
Min.
5000
50
100
200
50
100
200
Max.
660
270
500
1000
270
500
1000
0.1
0.2
192
TBD
Unit
ps
ps
ps
ps
ps
ps
ps
UI
UI
ps
ns
Bit Time
CML Output Rise Time 20
80% (CML Test Load)
[13]
SPDSEL = HIGH
SPDSEL = MID
SPDSEL = LOW
SPDSEL = HIGH
SPDSEL = MID
SPDSEL = LOW
t
FALL
CML Output Fall Time 80
20% (CML Test Load)
[13]
t
DJ
t
TJ
Deterministic Jitter (peak-peak)
[14, 17
Total Jitter (
σ
)
[15, 17]
0.2-1.0Gbps
1.0-1.5Gbps
t
TXLOCK
Transmit PLL lock to REFCLK
TBD
Receive Serial Inputs and CDR PLL Characteristics
Over the Operating Range
Parameter
t
RXLOCK
Description
Min.
Max.
10
2500
TBD
Unit
ms
UI
ns
ps
UI
Receive PLL Lock to Input Data Stream
Receive PLL Lock to Input Data Stream
Receive PLL Unlock Rate
Static Alignment
[16]
Error-free Window
[14, 17, 18]
t
RXUNLOCK
t
SA
t
EFW
Notes:
13. REFCLK has no phase or frequency relationship with RXCLK and only acts as a centering reference to reduce clock synchronization time. REFCLK must be
within
±
200- ppm (
±
0.02%) of the transmitter PLL reference (REFCLK) frequency, necessitating a
±
100-ppm crystal.
14. While sending continuous K28.5s, outputs loaded to a balanced 100
load, over the operating range.
15. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLK input, over the
operating range.
16. Static alignments is a measure of the alignment of the Receiver sampling point to the center of a bit. Static alignment is measured by sliding one bit edge in
3,000 nominal transitions until a character error occurs.
17. Receiver UI is calculated as 1/Fref*10 when RXRATE = LOW if no data is being received of the remote transmitter. If data is being received it is equal to
1/transmit serial bit rate.
18. Error Free Window is a measure of the time window between the bit centers where a transition may occur without causing a sampling error. It is measured
over the operational range.
TBD
0.75
相關(guān)PDF資料
PDF描述
CYP15G0402DXB Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器)
CYV15G0402DXB Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器)
CYP15G0403DXB Independent Clock Quad HOTLink II Transceiver(獨(dú)立時(shí)鐘，四熱連接II收發(fā)器)
CYV15G0403DXB Independent Clock Quad HOTLink II Transceiver(獨(dú)立時(shí)鐘，四熱連接II收發(fā)器)
CYW15G0403DXB Independent Clock Quad HOTLink II Transceiver(獨(dú)立時(shí)鐘，四熱連接II收發(fā)器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CYP15G0402DX-EVAL 功能描述:界面開(kāi)發(fā)工具 Quad Ch HOTLink II GbE 1XFC SERDES RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類(lèi)型:RS-485 工具用于評(píng)估:ADM3485E 接口類(lèi)型:RS-485 工作電源電壓:3.3 V
CYP15G0403DXB 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver Single 3.3V supply
CYP15G0403DXB_07 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Transceiver
CYP15G0403DXB_09 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver
CYP15G0403DXB_11 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver Single 3.3V supply
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*