參數(shù)資料
型號(hào)： CYP15G0402DX-BGI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Quad HOTLinkII SERDES
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, 1.52 MM HEIGHT, THERMALLY ENHANCED, BGA-256
文件頁(yè)數(shù)： 13/27頁(yè)
文件大?。?/td> 852K
代理商： CYP15G0402DX-BGI
CYP15G0402DX
PRELIMINARY
Document #: 38-02023 Rev. *B
Page 13 of 27
CYP15G0402DX Receive Data Path
Serial Line Receivers
A differential line receiver, INx
±,
is on each channel for
accepting a serial bit stream. The serial line receiver inputs are
differential needing only 100mv pp AC differential input. The
input can be DC- or AC-coupled to +3.3V powered fiber-optic
interface modules with a ECL/PECL output level. The input
could be AC-coupled to +5V powered optical modules. The
common-mode tolerance of these line receivers accommo-
dates a wide range of input signals.
The local loopback input (LPENx) for each channel allows the
serial transmit data for the associated channel to be routed
internally back to the clock and data recovery circuit
associated with that channel. When a channel is configured for
local loopback, the associated transmit serial driver outputs
are forced to output a differential logic-1. This prevents local
diagnostic patterns from being broadcast to attached remote
receivers or optical drivers.
Receive Channel Enabled
The CYP15G0402DX contains four receive channels that can
be independently enabled and disabled. Each channel can be
enabled or disabled separately through the BOE[7:0] inputs,
as controlled by the RXLE latch-enable signal. When RXLE is
HIGH, the signals present on the BOE[7:0] inputs are passed
through the Receive Channel Enable latch to control the PLLs
and logic of the associated receive channel. The BOE[7:0]
input associated with a specific receive channel is listed in
Table 2
.
When RXLE and BOE[x] are HIGH, the associated receive
channel is enabled to receive a serial stream from the selected
line receiver. When RXLE is HIGH and BOE[x] is LOW, the
associated receive channel is disabled and powered down.
Signal Detect
Each Line Receiver is simultaneously monitored for:
analog amplitude
transition density
received data stream outside normal frequency range
(±200 ppm).
All of these conditions must be valid for the Signal Detect block
to indicate a valid signal is present. This status is presented on
the LFIx (Link Fault Indicator) output associated with each
receive channel. These LFIx outputs change synchronous to
the receive interface recovered clock.
While the majority of these signal monitors are based on fixed
constants, the analog amplitude level detection is adjustable
to allow operation with attenuated signals. This adjustment is
made through the SDASEL signal, a 3-level select
[1]
input,
which sets the trip point for the detection of a valid signal at
one of three levels, as listed in
Table 4
. SDASEL input controls
the analog monitors for all receive channels.
Clock/Data Recovery
The extraction of a bit-rate clock and recovery of bits from each
received serial stream is performed by a separate Clock/Data
Recovery (CDR) block within each channel. The clock
extraction function is performed by embedded phase-locked
loops that track the frequency and phase of transitions of the
incoming bit streams.
Each CDR accepts a character-rate or half-character-rate
reference clock on the REFCLK
±
input. This REFCLK
±
input
is used to ensure that the VCO is operating at the correct
frequency. The use of the REFCLK improves PLL acquisition
time, and limits the unlocked frequency excursions of the VCO
when there is no input data.
Regardless of the type of input signal, the CDR will attempt to
recover a data stream. If the frequency of the recovered data
stream is outside the limits set by the integrated range
controls, the PLL reference will switch to REFCLK. When the
frequency of the selected data stream returns to a valid
frequency, the CDR PLL is allowed to track the received data
stream. The frequency of REFCLK is required to be within
±
200 ppm of the frequency of the clock that drives the REFCLK
signal of the
remote
transmitter to ensure a lock to the
incoming data stream.
Deserializer/Framer
Each CDR circuit extracts bits from the associated serial data
stream and clocks these bits into the Shifter/Framer at the
bit-clock rate. When enabled, the Framer examines the data
stream looking for one or more COMMA or K28.5 characters
at all possible bit positions. The location of this character in the
data stream is used to determine the frame of the characters
that follow.
Framing Character
The CYP15G0402DX allows selection of one of three combi-
nations of framing characters to support requirements of
different interfaces. The selection of the framing character is
made through the FRAMCHAR input.
FRAMCHAR is a 3-level select
[1]
input that allows selection of
one of three different characters or character combinations.
These combinations are listed in
Table 5
.
Framer
The framer on each channel operates in one of three different
modes, as selected by the RFMODE input. When RFMODE is
LOW, the low-latency framer is selected. This framer operates
by stretching the recovered character clock until it aligns with
the character boundaries. In this mode the framer aligns on the
first detection of the selected framing character.
When RFMODE is MID the Cypress-mode multi-character
framer is selected. The detection of multiple framing
Table 4. Analog Amplitude Detect Valid Signal Levels
SDASEL
Typical Signal with Peak Amplitudes
Above
LOW
140 mV p-p differential
MID (Open)
280 mV p-p differential
HIGH
420 mV p-p differential
Table 5. Framing Character Selector
FRAMCHAR
Bits Detected in Framer
Character Name
Bits Detected
LOW
+COMMA
00111110XX
MID (Open)
+COMMA
COMMA
00111110XX or
11000001XX
HIGH
+K28.5
K28.5
0011111010 or
1100000101
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