參數(shù)資料
型號(hào)： CYP15G0402DX-BGI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Quad HOTLinkII SERDES
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, 1.52 MM HEIGHT, THERMALLY ENHANCED, BGA-256
文件頁(yè)數(shù)： 18/27頁(yè)
文件大?。?/td> 852K
代理商： CYP15G0402DX-BGI
CYP15G0402DX
PRELIMINARY
Document #: 38-02023 Rev. *B
Page 18 of 27
Differential CML Serial Outputs: OUTA
±
, OUTB
±
,
OUTC
±
, OUTD
±
V
OHC
Output HIGH Voltage
Typical
V
CC
0.5
V
CC
0.5
V
CC
1.1
V
CC
1.1
450
560
Max
Unit
V
V
V
V
mV
mV
100
differential load
150
differential load
100
differential load
150
differential load
100
differential load
150
differential load
V
CC
0.2
V
CC
0.2
V
CC
0.7
V
CC
0.7
800
1000
V
OLC
Output LOW Voltage
V
ODIF
Output Differential Voltage
|(OUT+)
(OUT
)|
Differential Serial Line Receiver Inputs: INA
±
, INB
±
, INC
±
, IND
±
VI
DIFF]
Input Differential Voltage
|(IN+)
(IN
)|
V
IHE
Highest Input HIGH Voltage
V
ILE
Lowest Input LOW Voltage
I
IHE
Input HIGH Current
I
ILE
Input LOW Current
Iv
com[10]
Input common mode range
100
1200
mV
V
CC
V
V
μ
A
μ
A
V
V
CC
2.0
V
IN
= V
IHH
Max.
V
IN
= V
ILL
Min.
((Vcc-2.0)+.05)min.,
((Vcc-.05)max.
1000
700
1.25
3.25
Miscellaneous
I
CC[11]
Typical
860
TBD
Max.
1100
TBD
Unit
mA
mA
Power Supply Current
Commercial
Industrial
CYP15G0402DX Transmitter LVTTL Switching Characteristics
Over the Operating Range
Parameter
f
TS
t
TXCLK
t
TXCLKH
t
TXCLKL
t
TXCLKR [12]
t
TXCLKF[12]
t
TXDS
t
TXDH
f
TOS
t
TXCLKO
t
TXCLKOD
t
TXCLKOD
t
TXODS
t
TXODH
t
TXRSS
t
TXRSH
Notes:
10. This is the minimum difference in voltage between the true and the complement input required to ensure detection of a logic 1 or logic 0. A logic true occurs
when the input + is above the -input. A logic zero is true when the +input is below the voltage of - input.
11.
Maximum current is measured with V
= MAX, RFEN = LOW, with all serial channels sending a constant alternations 01 pattern, and the output unloaded.
Typical is measured under same conditions, except that power is 3.3V.
12. Paralleled data output specifications are only valid if all outputs are loaded with similar DC and AC loads.
Description
Min.
20
6.66
2.2
2.2
0.3
0.3
2
1
20
6.66
-0.7
-0.0
1.5
1.5
3
1
Max.
150
50
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
TXCLKx Clock Cycle Frequency
TXCLKx Period
TXCLKx HIGH Time
TXCLKx LOW Time
TXCLKx Rise Time
TXCLKx Fall Time
Transmit Data Set-Up Time to
TXCLKx
↑
(TXCKSEL
≠
LOW)
Transmit Data Hold Time from TXCLKx
↑
(TXCKSEL
≠
LOW)
TXCLKO Clock Cycle Frequency equals 1x or 2x REFCLK Frequency
TXCLKO Period
TXCLKOP Duty Cycle Centered with 60 per cent high time
TXCLKON Duty Cycle Centered with 40 per cent high time
Transmit Data Set-Up Time to
TXCLKO
↑
(TXCKSEL
=
LOW)
Transmit Data Hold Time from TXCLKO
↑
(TXCKSEL
=
LOW)
TXRST Set-Up Time to
TXCLKO
↑
TXRST Hold Time from
TXCLKO
↑
1.7
1.7
150
50
+0.7
1.5
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參數(shù)描述
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