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參數(shù)資料
| 型號： | CYP15G0402DX-BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Quad HOTLinkII SERDES |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.52 MM HEIGHT, THERMALLY ENHANCED, BGA-256 |
| 文件頁數(shù)： | 27/27頁 |
| 文件大?。?/td> | 852K |
| 代理商： | CYP15G0402DX-BGI |
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CYP15G0402DX
PRELIMINARY
Document #: 38-02023 Rev. *B
Page 27 of 27
Document Title: CYP15G0402DX Quad HOTLinkII
SERDES
Document Number: 38-02023
Issue
Date
**
108363
07/11/01
*A
108915
07/31/01
*B
112986
03/01/02
REV.
ECN NO.
Orig. of
Change
TME
AMV
TPS
Description of Change
New Data Sheet
Changed name of part from PHY to SERDES
Changed common mode input specs to match 401D part pp. 17, 18
Added engineering changes to half-rate timing. p. 22
Updated the spec as per meeting with engineering pp. 20
–
23
Changed the Refclock input to VLTTL both inputs p. 9
Addition of TXCLKO N and the TXCLKO P specs p. 22
Changed the TXCLKO clock output to reflect the new timing p. 22
Changed the Half Clock drawing so that the valid time was at clock edges
Changed the input power input p. 21, p. 22 max. power
Changed the spec for serial output levels at the different terminations.
Changed the common mode input range of serial input
Increased the serial input current under the conditions of V
CC
and min.
Added to the duty cycle of transmit and receiver clock signals
Changed rise time of the serial inputs and receiver
Changed half-rate timing drawing from not valid at clock edges to valid at
clock edges
Max. voltage reduced from 4.2 to 3.8
Matched the common specs with the family of parts pp. 21
–
24
Changed max output current to 35 Ma p. 20
Corrected period timing of min. clock from 100 ns to 50 ns p. 19
Added
“
Preliminary
”
Added pin RXCKSEL to the pin layout p. 6, 7 to pin layout and pin descriptions
Change min. clock frequency
Change the front pages
Remove decoder command from p. 16, as it is no longer used.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYP15G0402DXB | Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器) |
| CYV15G0402DXB | Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器) |
| CYP15G0403DXB | Independent Clock Quad HOTLink II Transceiver(獨立時鐘，四熱連接II收發(fā)器) |
| CYV15G0403DXB | Independent Clock Quad HOTLink II Transceiver(獨立時鐘，四熱連接II收發(fā)器) |
| CYW15G0403DXB | Independent Clock Quad HOTLink II Transceiver(獨立時鐘，四熱連接II收發(fā)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0402DX-EVAL | 功能描述:界面開發(fā)工具 Quad Ch HOTLink II GbE 1XFC SERDES RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| CYP15G0403DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver Single 3.3V supply |
| CYP15G0403DXB_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Transceiver |
| CYP15G0403DXB_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver |
| CYP15G0403DXB_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver Single 3.3V supply |
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