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參數(shù)資料
| 型號： | CYP15G0402DX-BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Quad HOTLinkII SERDES |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.52 MM HEIGHT, THERMALLY ENHANCED, BGA-256 |
| 文件頁數(shù)： | 16/27頁 |
| 文件大小： | 852K |
| 代理商： | CYP15G0402DX-BGI |
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CYP15G0402DX
PRELIMINARY
Document #: 38-02023 Rev. *B
Page 16 of 27
clock boundaries are not adjusted, and COMDETx may be
active during the rising edge of RXCLKx
–
.
Parity Generation
In addition to the ten data and COMDETx status bits that are
output on each channel, an RXOPx output is also available on
that channel. The CYP15G0402DX to supports ODD parity
generation for each channel. To handle a wide range of system
environments, the CYP15G0402DX supports two forms of
parity and no parity.
parity on the RXDx[9:0] character
parity on the RXDx[9:0] character and COMDETx status.
These modes differ in the number bits which are included in
the parity calculation. Only ODD parity is provided which
ensures that at least one bit of the data bus is always a logic-1.
Those bits covered by parity generation are listed in
Table 9
.
Parity generation is enabled through the 3-level select
PARCTL input. When PARCTL is LOW, parity checking is
disabled, and the RXOPx outputs are all disabled (High-Z).
When PARCTL is MID, ODD parity is generated for the
RXDx[9:0] bits.
When PARCTL is HIGH, ODD parity is generated for both the
RXDx[9:0] bits and the associated COMDETx signal.
JTAG Support
The CYP15G0402DX contains a JTAG port to allow system
level diagnosis of device interconnect. Of the available JTAG
modes, only boundary scan is supported. This capability is
present only on the LVTTL inputs and outputs and REFCLK.
The high-speed serial signals are not part of the JTAG test
chain.
JTAG ID
The JTAG device ID for the CYP15G0402DX is
‘
0C801069
’
hex.
3-Level Select Inputs
Each 3-Level select input reports as two bits in the scan
register. These bits report the LOW, MID, and HIGH state of
the associated input as 00, 10, and 11, respectively.
Table 9. Output Register Parity Generation
Signal Name
Receive Parity Generate Mode (PARCTL)
LOW
[7]
MID
HIGH
X
[8]
COMDETx
RXDx[0]
X
X
RXDx[1]
X
X
RXDx[2]
X
X
RXDx[3]
X
X
RXDx[4]
X
X
RXDx[5]
X
X
RXDx[6]
X
X
RXDx[7]
X
X
RXDx[8]
X
X
RXDx[9]
X
X
Notes:
7.
8.
Receive path parity output drivers are disabled when PARCTL is LOW.
When BIST is not enabled,COMDETx is usually driven to a logic 0, but
will be driven HIGH when the character in the output buffer is the selected
framing character.
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| CYP15G0402DXB | Quad HOTLink II SERDES(四HOTLink II并行轉(zhuǎn)換器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0402DX-EVAL | 功能描述:界面開發(fā)工具 Quad Ch HOTLink II GbE 1XFC SERDES RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| CYP15G0403DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver Single 3.3V supply |
| CYP15G0403DXB_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Transceiver |
| CYP15G0403DXB_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver |
| CYP15G0403DXB_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver Single 3.3V supply |
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