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參數(shù)資料
| 型號(hào)： | CY7C954DX |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | ATM HOTLink Transceiver(ATM 熱接插收發(fā)器) |
| 中文描述： | 自動(dòng)柜員機(jī)的HOTLink收發(fā)器（自動(dòng)柜員機(jī)熱接插收發(fā)器） |
| 文件頁數(shù)： | 6/42頁 |
| 文件大?。?/td> | 484K |
| 代理商： | CY7C954DX |
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CY7C954DX
PRELIMINARY
6
10
RXFULL*
3-state TTL output,
changes following
RXCLK
↑
Receive FIFO Full Flag.
Active LOW when configured for UTOPIA timing (EXTFIFO is LOW), active
HIGH when configured for Cascade timing (EXTFIFO is HIGH).
In Receive mode (11), when the Receive FIFO is addressed, RXFULL* is
asserted one RXCLK cycle after the address match, when the Receive FIFO
has room for four or fewer writes. If the RXCLK input is not continuous, or if the
FIFO is accessed at a rate slower than data is being received, RXFULL* may
indicate loss of data.
This output is not used in Receive modes (00, 01, 10).
Receive FIFO Cell Available Flag.
This signal is asserted (LOW) when the Receive FIFO contains at least one
ATM cell ready to be read. It is asserted one RXCLK cycle after the device
RXADDR[2:0] address matches ADDRSEL[2:0] and selected by RXEN*.
RXCLAV is forced to the High-Z state only during a
“
full-chip
”
reset (i.e., while
RESET* is LOW) or on the cycle after an
“
unmatch
”
in RXADDR[2:0]. (Used
for polling FIFO status.)
Receive FIFO Empty Flag.
Active LOW when configured for UTOPIA timing (EXTFIFO is LOW), active
HIGH when configured for Cascade timing (EXTFIFO is HIGH).
In Receive mode (11), when the Receive FIFO is enabled, RXEMPTY* is as-
serted one RXCLK cycle after the address match, when no data remains in the
Receive FIFO. Any read operation occurring when RXEMPTY* is asserted
results in no change in the FIFO status, and the data from the last valid read
remains on the RXDATA bus.
This output functions the same RXCLAV in Receive modes (00, 01, 10).
Receive FIFO Reset.
When the Receive FIFO is addressed and RXRST* is sampled while asserted
(LOW) for eight or more RXCLK cycles, along with the deassertion of RXEN*
and an address match condition existing, a Receive FIFO reset is initiated.
Reframe Enable.
Used to control when the framer is allowed to adjust the character boundaries
based on detection of one or more K28.5 characters in the data stream. When
HIGH, the framer is allowed to adjust the character boundaries relative to re-
ceived serial data stream. When LOW, the boundary is fixed.
Receiver BIST Enable.
When active, the receiver is configured to perform a character-for-character
match of the incoming data stream with a 511-character BIST sequence. The
result of character mismatches are indicated on RXRVS. Completion of each
511-character BIST loop is accompanied by an assertion pulse on the
RXFULL* flag.
19
RXCLAV
3-state TTL output,
changes following
RXCLK
↑
21
RXEMPTY*
3-state TTL output,
changes following
RXCLK
↑
67
RXRST*
TTL input, sampled
on
RXCLK
↑
,
Internal Pull-Up
73
RFEN
TTL input,
asynchronous,
Internal Pull-Up
77
RXBISTEN*
TTL input,
asynchronous,
Internal Pull-Up
Control Signals
6
LOOPTX
TTL asynchronous
input,
Internal Pull-Down
Serial-in to Serial-out LOOP Select.
This input controls the LOOP-through function in which the serial data is re-
covered by the Clock/Data Recovery PLL and then is retransmitted using the
Transmitter PLL as the bit-rate reference. It selects between the output of the
Transmitter FIFO and the output of the Elasticity buffer as the input to the
Transmit Encoder. When LOW, the transmit FIFO is the source of data for
transmission. When HIGH, the Elasticity Buffer is the source of data for trans-
mission.
Pin Descriptions
(continued)
CY7C954DX HOTLink Transceiver
Pin #
Name
I/O Characteristics
Signal Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C964A | Bus Interface Logic Circuit |
| CY7C964A-UM | Bus Interface Logic Circuit |
| CY7C964A-UMB | Bus Interface Logic Circuit |
| CY7C964A-ASC | Bus Interface Logic Circuit |
| CY7C964A-NC | Bus Interface Logic Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C955-NC | 制造商:Cypress Semiconductor 功能描述:SONET Transceiver, AX ATM-SONET/SDH Transceiver |
| CY7C960-UMB | 制造商:Cypress Semiconductor 功能描述: |
| CY7C9611-NC | 功能描述:IC PHYSICAL LAYER DEVICE RoHS:否 類別:未定義的類別 >> 其它 系列:* 標(biāo)準(zhǔn)包裝:1 系列:* 其它名稱:MS305720A |
| CY7C964A-GMB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C964AUM | 制造商: 功能描述: 制造商:CY 功能描述: 制造商:undefined 功能描述: |
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