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參數(shù)資料
| 型號： | CY7C954DX |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | ATM HOTLink Transceiver(ATM 熱接插收發(fā)器) |
| 中文描述： | 自動柜員機(jī)的HOTLink收發(fā)器（自動柜員機(jī)熱接插收發(fā)器） |
| 文件頁數(shù)： | 13/42頁 |
| 文件大?。?/td> | 484K |
| 代理商： | CY7C954DX |
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CY7C954DX
PRELIMINARY
13
the contents of the Transmit FIFO
the contents of the Elasticity Buffer
the state of the transmitter BIST enable (TXBISTEN*)
These signals are used by the Transmit Control State Machine
to control the data formatter, read access to the Transmit FIFO
and Elasticity Buffer, the Byte-Packer, and BIST. They deter-
mine the content of the characters passed to the Encoder and
Transmit Shifter.
Elasticity Buffer
A short (8-character) FIFO is contained between the receive
and transmit paths. This FIFO is used to separate the time
domains of the received serial data stream and the outbound
transmit data stream. This permits retransmission of received
data without worry of jitter gain or jitter transfer. This allows
error-free transmission of the same data, when configured in
daisy-chain or ring configurations, to an unlimited number of
destinations.
This Elasticity Buffer is enabled when the LOOPTX input is
asserted HIGH. This directs the receiver to place all non-C5.0
(K28.5) characters into the Elasticity Buffer. LOOPTX also di-
rects the Transmit Control State Machine to read data from the
Elasticity Buffer instead of from the Transmit FIFO.
While retransmitting data from the Elasticity Buffer, the Trans-
mit FIFO is available for preloading of data to be transmitted.
Once LOOPTX is deasserted (LOW), normal data transmis-
sion from the Transmit FIFO resumes.
Serial Line Receivers
Two differential line receivers, INA± and INB±, are available for
accepting serial data streams, with the active input selected
using the A/B* input.
The DLB[1:0] inputs allow the transmit Serializer output to be
selected as a third input serial stream (DLB[1:0]=01 is the di-
agnostic loopback function). The serial line receiver inputs are
all differential, and will accommodate wire interconnect with
filtering losses or transmission line attenuation greater than
9 dB (V
DIF
> 200 mV, or 400 mV peak-to-peak differential) or
can be directly connected to +5V fiber-optic interface modules
with appropriate terminations (any ECL logic family, not limited
to ECL 100K). The common-mode tolerance of these line re-
ceivers accommodates a wide range of signal termination volt-
ages. Input levels less than about 300 mV will cause LFI* to be
asserted LOW, indicating a line fault, but the input should still
decode data correctly.
As can be seen in
Table 2
, these inputs are configured to allow
single-pin control for most applications. For those systems re-
quiring selection of only INA± or INB±, the DLB[1:0] signals
can be tied LOW, and the A/B selection can be performed us-
ing only A/B*. For those systems requiring only a single input
and a local loopback, the A/B* can be tied HIGH or LOW,
DLB[1] signal can be tied LOW and DLB[0] can be used for
loopback control.
The level-restored (10) and reclocked (11) settings make use
of one of the transmit data outputs. When configured for level-
restored or reclocked data, the selected input is retransmitted
on OUTB±. The level-restored connection simply buffers the
input signal allowing a
“
bus-like
”
connection to be constructed
without concern for multi-drop PECL signal layout issues.
The reclocked connection buffers a PLL-filtered copy of the
selected input data stream. This removes most of the high-
frequency jitter that accumulates on a signal when sent over
long transmission lines. Unlike data retransmitted from the
Elasticity Buffer, the output data stream is clocked by a recov-
ered clock, not by a derivative of the local REFLCK input. This
allows a data source to provide data to multiple recipients, but
can suffer from jitter peaking when communicated through
several PLLs. The reclocked connection may be required
when sending non-8B/10B coded data streams, or data
streams that cannot tolerate the data forwarding policies of the
Elasticity Buffer.
This reclocked output stream may also be beneficial in sys-
tems requiring very low latency. The internal data delays for a
reclocked serial stream are a small number of bits, while data
sent through the Elasticity Buffer incurs a delay of a small num-
ber of characters.
Signal Detect
The selected Line Receiver (that routed to the clock and data
recovery PLL) is simultaneously monitored for:
analog amplitude (>400 mV pk-pk) on selected input,
transition density,
received data stream outside normal frequency range
(±400 ppm),
and carrier detected.
All of these conditions must be valid for the Signal Detect block
to indicate a valid signal is present. This status is presented on
the LFI* (Link Fault Indicator) output, which changes synchro-
nous to RXCLK. While link status is monitored internally at all
times, it is necessary to have transitions on RXCLK to allow
this signal to change externally.
Clock/Data Recovery
The extraction of a bit-rate clock and recovery of data bits from
the received serial stream is performed within the Clock/Data
Recovery (CDR) block. The clock extraction function is per-
formed by a high-performance embedded phase-locked loop
(PLL) that tracks the frequency of the incoming bit stream and
aligns the phase of its internal bit-rate clock to the transitions
in the serial data stream.
The CDR makes use of the clock present at the REFCLK input.
It is used to ensure that the VCO (within the CDR) is operating
at the correct frequency (rather than some harmonic of the bit
rate), to improve PLL acquisition time, and to limit unlocked
frequency excursions of the CDR VCO when no data is
present at the serial inputs.
Regardless of the type of signal present, the CDR will attempt
to recover a data stream from it. If the frequency of the recov-
ered data stream is outside the limits for the range controls,
the CDR PLL will track REFCLK instead of the data stream.
When the frequency of the selected data stream returns to a
Table 3. Speed Select and Range Select Settings
SPDSEL
LOW
LOW
HIGH
HIGH
RANGESEL
LOW
HIGH
LOW
HIGH
Serial
Data Rate
(MBaud)
50
–
100
50
–
100
100
–
200
100
–
200
REFCLK
Frequency
(MHz)
10
–
20
20
–
40
10
–
20
20
–
40
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