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參數(shù)資料
| 型號： | CY7C954DX |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | ATM HOTLink Transceiver(ATM 熱接插收發(fā)器) |
| 中文描述： | 自動柜員機的HOTLink收發(fā)器（自動柜員機熱接插收發(fā)器） |
| 文件頁數(shù)： | 25/42頁 |
| 文件大?。?/td> | 484K |
| 代理商： | CY7C954DX |
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CY7C954DX
PRELIMINARY
25
CY7C954DX HOTLink Transceiver Operation
The interconnection of two or more CY7C954DX Transceivers
form a general-purpose communications subsystem capable
of transporting user data at up to 20 MBytes per second over
several types of serial interface media. The CY7C954DX is
highly configurable with multiple modes of operation.
In the transmit section of the CY7C954DX, data moves from
the input register, through the Transmit FIFO, to the 8B/10B
encoder. The encoded data is then shifted serially out the
OUTx± differential PECL compatible drivers. The bit-rate clock
is generated internally from a 2.5x, 5x, or 10x PLL clock mul-
tiplier. A more complete description is found in the section
CY7C954DX HOTLink Transmit-Path Operating Mode De-
scription
.
In the receive section of the CY7C954DX, serial data is sam-
pled by the receiver on one of the INx± differential line receiver
inputs. The receiver clock and data recovery PLL locks onto
the selected serial bit stream and generates an internal bit-rate
sample clock. The bit stream is deserialized, decoded, and
presented to the Receive FIFO, along with a character clock.
The data in the FIFO can then be read either slower or faster
than the incoming character rate. A more complete description
is found in the section
CY7C954DX HOTLink Receive-Path
Operating Mode Description
.
The Transmitter and Receiver parallel interface timing and
functionality can be configured to be a UTOPIA level I or II
compliant interface, or for single PHY (point-to-point interfac-
es) to Cascade directly to external FIFOs for depth expansion.
The HOTLink Transceiver serial interface provides a seamless
interface to various types of media. A minimal number of ex-
ternal passive components are required to properly terminate
transmission lines and provide PECL loads. For power supply
decoupling, a single capacitor (in the range of 0.02
μ
F to
0.1
μ
F) is required per power/ground pair. Additional informa-
tion on interfacing these components to various media can be
found in the
“
HOTLink Design Considerations
”
application
note.
CY7C954DX HOTLink Transmit-Path
Operating Mode Descriptions
The HOTLink Transmitter data interface is an asynchronous
parallel data register, enabled by a match between the
TXADDR[2:0] and the strapped value on ADDRSEL[2:0], and
qualified by TXEN.
Input Register Mapping
TXDATA input bus is mapped into characters including a
TXSOC and TXSVS bit for protocol mapping, eight bits of data
and a TXSC/D* bit to select either control or data characters.
If the TXSVS bit is HIGH (and either TXSOC or TXSC/D* is
LOW), an SVS (C0.7) character is passed to the encoder, re-
gardless of the contents of the other TXDATA inputs. If the
TXSVS bit is LOW, the associated TXDATA character is encod-
ed per the remaining bits in that character.
When TXSOC is LOW, the TXSC/D* bit controls the encoding
of the data bits TXDATA[7:0] of each character. It is used to
identify if the input character represents data or a Special
Character code. If the TXSC/D* input is LOW, the character is
encoded using the Data Character codes listed in
Table 8
. If
the TXSC/D* input is HIGH, the character is encoded using the
Special Character codes listed in
Table 9
.
This input structure allows transmission of normal data
streams, while offering the added benefits of three types of
embedded cell markers. The Serializer operates synchronous
to REFCLK, which is multiplied by 10 to generate the serial
data bit-clock.
Embedded Cell Marker
Embedded cell markers are used to mark the start of cells or
frames of information passed from one end of the link to the
other. These markers are set by asserting TXSOC HIGH, with
TXSC/D* and TXSVS in combinations of HIGH or LOW (see
Table 1
), along with the remaining data on the TXDATA bus.
When the character accompanying this marker is read from
the output end of the Transmit FIFO, a C8.0 (K23.7), C9.0
(K27.7), or C10.0 (K29.7) character is inserted into the data
stream prior to the following data characters being read from
the Transmit FIFO.
CY7C954DX HOTLink Receive-Path
The HOTLink Receiver is a Serial-in to Parallel-out converter
with some data processing capability.
In this mode, serial data is received at one of the differential
line receiver inputs and routed to the Deserializer and Framer.
The PLL in the clock and data recovery block is used to extract
a bit-rate clock from the transitions in the data stream, and
uses that clock to capture bits from the serial stream. These
bits are passed to the Deserializer where they are formed into
10-bit characters.
To align the incoming bit stream to the proper character bound-
aries, the Framer must be enabled by asserting RFEN HIGH.
The Framer logic-block checks the incoming bit stream for the
unique pattern that defines the character boundaries. This log-
ic filter looks for the ANSI X3.230 symbol defined as a
“
Special
Character Comma
”
(K28.5 or C5.0). Once a K28.5 is found,
the Framer captures the offset of the data stream from the
present character boundaries, and resets the boundary to re-
flect this new offset, thus framing the data to the correct char-
acter boundaries.
Since noise-induced errors can cause the incoming data to be
corrupted, and since many combinations of corrupt and legal
data can create an aliased K28.5, the framer may also be dis-
abled by deasserting RFEN LOW.
An option exists in the framer to require multiple K28.5 char-
acters, meeting specific criteria, before the character bound-
aries are reset. This multi-byte mode of the Framer is enabled
by keeping RFEN asserted HIGH for greater than approxi-
mately 2000 character clock cycles. For multi-byte framing, the
receiver must find a pair of K28.5 characters, both on identical
10-bit boundaries, within a 5-character span (50 bits).
The deserializer operates synchronous to the recovered bit-
clock, which is divided by 10 to generate the Receive FIFO
write clock. Data words are read from the Receive FIFO, using
the external RXCLK input, when addressed by RXADDR[2:0]
matching ADDRSEL[2:0] and selected by RXEN*.
Embedded Cell Marker
Three types of embedded cell marker are available to mark the
start of cells or frames of information passed from one end of
the link to the other. When a C8.0 (K23.7) character is detected
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