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參數(shù)資料
| 型號(hào)： | CY7C954DX |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | ATM HOTLink Transceiver(ATM 熱接插收發(fā)器) |
| 中文描述： | 自動(dòng)柜員機(jī)的HOTLink收發(fā)器（自動(dòng)柜員機(jī)熱接插收發(fā)器） |
| 文件頁數(shù)： | 27/42頁 |
| 文件大?。?/td> | 484K |
| 代理商： | CY7C954DX |
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CY7C954DX
PRELIMINARY
27
moval of stale data from the Transmit FIFO, it may also be reset
during a BIST operation. The reset operation proceeds as doc-
umented, with the exception of the information presented on
the TXEMPTY* FIFO status flag. Since this flag is used to
present BIST loop status, it will reflect the state of the transmit
BIST loop status until TXBISTEN* is no longer recognized in-
ternally. The completion of the reset operation may still be
monitored through the TXFULL* FIFO status flag.
The TXEMPTY* flag, when used for transmit BIST progress
indication, continues to reflect the active HIGH or active LOW
settings determined by the UTOPIA or Cascade timing model
selected by the EXTFIFO input.; i.e., when configured for the
Cascade timing model, the TXEMPTY and TXFULL FIFO
flags are active HIGH, when configured for the UTOPIA timing
model the TXEMPTY* and TXFULL* FIFO flags are active
LOW.
Figure 5
uses the UTOPIA conventions for the illustra-
tion.
When TXBISTEN* is first recognized, the TXEMPTY* flag is
clocked to a reset state, regardless of the addressed state of
the Transmit FIFO (if TXADDR[2:0] matches ADDRSEL[2:0] or
not), but is not driven out of the part unless the MATCH has
been sampled TRUE. Following this, on each completed pass
through the BIST loop, the TXEMPTY* flag is set for one
TXCLK period.
The TXEMPTY* flag remains set until the interface is ad-
dressed and the state of TXEMPTY* has been observed. If the
device is not addressed (if TXADDR[2:0] does not match
ADDRSEL[2:0]), the flag remains set internally regardless of
the number of TXCLK clock cycles that are processed. If the
device status is not polled on a sufficiently regular basis, it
possible for the host system to miss some of these BIST loop
indications.
A pass through the loop is defined as that condition where the
encoder generates the D0.0 state. Depending on the initial
state of the BIST LFSR, the first pass through the loop may
occur at substantially less than 511 character periods. Follow-
ing the first pass, as long as TXBISTEN* remains LOW, all
remaining passes are exactly 511 characters in length.
BIST Receive Path
The receive path operation in BIST is similar to that of the
transmit path. When RXBISTEN* is recognized internally, all
writes to the Receive FIFO are suspended. If the receive data
state machine was in the middle of processing a multi-charac-
ter sequence or other atomic operation (e.g., a start of cell
marker and its associated data), the characters associated
with the atomic operation are discarded and not written to the
Receive FIFO.
Any data present in the Receive FIFO when RXBISTEN* is
recognized remains in the FIFO but is NOT available for read-
ing through the host parallel interface until the BIST operation
is complete. This is because the error output indicator for re-
ceive BIST operations is the RXRVS pin, which is normally
associated with the RXDATA bus. To prevent read operations
while BIST is in operation, the RXEMPTY* and RXCLAV flags
are forced to indicate an Empty condition. Once RXBISTEN*
has been removed and recognized internally, the Receive
FIFO status flags are updated to reflect the current content
status of the Receive FIFO.
To allow removal of stale data from the Receive FIFO, it may
be reset during a BIST operation. The reset operation pro-
ceeds as documented, with the exception that the RXEMPTY*
and RXCLAV status flags already indicate an empty condition.
The RXFULL* flag is used to present BIST progress. The ac-
tive (asserted) state on RXFULL* (and RXEMPTY*) remain
controlled by the present operating mode and interface timing
model (UTOPIA or Cascade).
When RXBISTEN* has been recognized, RXFULL* becomes
the receive BIST loop indicator. When RXBISTEN* is first rec-
ognized, the RXFULL* flag is clocked to a set state, regardless
of the addressed state of the Receive FIFO (regardless of the
match between TXADDR[2:0] and ADDRSEL[2:0]). Following
this, RXFULL* remains set until the receiver detects the start
of the BIST pattern. Then RXFULL* is deasserted for the du-
ration of the BIST pattern, pulsing asserted for one RXCLK
period on the last symbol of each BIST loop. If 14 of 28 con-
secutive characters are received in error, RXFULL* returns to
the set state until the start of a BIST sequence is again de-
tected.
Just like the BIST status flag on the transmit data path, the
RXFULL* flag captures the asserted states, and keeps them
until they are read. This means that if the status flag is not read
on a regular basis, events may be lost.
The detection of errors is presented on the RXRVS output.
Unlike the RXFULL* FIFO status flag, the active state of this
outputs is not controlled by the EXTFIFO input. With the Re-
ceive FIFO enabled, this output will operate the same as the
RXFULL* flag, with respect to preserving the detection state
of an error until it is read. An error indication that occurs while
the RXEN* is deasserted will be
“
remembered
”
until RXEN* is
asserted.
Unlike the RXFULL* flag, which only needs the CY7C954DX
to be addressed (RXADDR[2:0] matching ADDRSEL[2:0]
sampled TRUE by RXCLK) to enable the RXFULL* three-state
driver, and an RXCLK to
“
read
”
the flag, the RXRVS output
requires a selection (assertion of RXEN* while addressed) to
enable the RXDATA bus three-state drivers. The selection pro-
cess is necessary to ensure that a multi-PHY implementation
does not enable two drivers onto the RXRVS output at the
same time.
Bus Interfacing
The parallel transmit and receive host interfaces to the
CY7C954DX are configurable. The choices are UTOPIA or
Cascade control modes.
Both modes have internal Transmit and Receive FIFOs which
can be written or read at any rate up to the maximum 50-MHz
clock rate of the FIFOs. Internal operations of the CY7C954DX
do not use the external TXCLK or RXCLK, but instead make
use of REFCLK for transmit path operations and a recovered
character clock for receive path operations.
The UTOPIA timing model is based on the ATM Forum
UTOPIA interface standards. This timing model is that of a
FIFO with active LOW FIFO status flags and read/write en-
ables.
The Cascade timing model is a modification of the UTOPIA
configuration that changes the flags and FIFO read/write en-
ables to active HIGH. This model is present primarily to allow
depth expansion of the internal FIFO by direct coupling to ex-
ternal CY7C42x5 synchronous FIFOs. To allow this direct cou-
pling, the cycle-to-cycle timing between the transmit and re-
ceive enables (TXEN* and RXEN*) are also modified to ensure
correct data transfer.
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