參數(shù)資料
型號： CY7C954DX
廠商： Cypress Semiconductor Corp.
英文描述： ATM HOTLink Transceiver(ATM 熱接插收發(fā)器)
中文描述： 自動柜員機的HOTLink收發(fā)器（自動柜員機熱接插收發(fā)器）
文件頁數(shù)： 31/42頁
文件大?。?/td> 484K
代理商： CY7C954DX
CY7C954DX
PRELIMINARY
31
eight consecutive clock cycles. Any disruption of the reset se-
quence prior to reaching the eight cycle count, either by re-
moval of the TXADDR[2:0] or RXADDR[2:0] matches with
ADDRSEL[2:0] or the respective TXRST* or RXRST*, or as-
sertion of the associated TXEN* or RXEN*, terminates the se-
quence and does not reset the FIFO. Because the
TXADDR[2:0] or RXADDR[2:0] matching ADDRSEL[2:0] must
remain asserted during the reset sequence, the addressed
FIFO flags remain driven during the entire sequence.
The FIFO Reset sequence will remove any pre-existing ad-
dress match condition and TXEN* or RXEN* will need to be
deasserted for one clock cycle before address match can be
re-established.
Transmit FIFO Reset Sequence
The Transmit FIFO reset sequence is started when TXRST* is
sampled LOW and TXADDR[2:0] matches ADDRSEL[2:0] on
the rising edge of TXCLK. However, if TXEN* is asserted, the
reset sequence is inhibited until it is removed (TXEN* is sam-
pled HIGH for UTOPIA timing or LOW for Cascade timing).
Because a Tx_RstMatch condition is present, the Transmit
FIFO flags are asserted and can be used to track the status of
any Transmit FIFO reset in progress. Once the reset sequence
has reached its maximum count, the Transmit FIFO flags are
forced to indicate a FULL* condition (TXCLAV is deasserted,
and TXFULL* is asserted). This indicates that the Transmit
FIFO reset has been recognized by the Transmit Control State
Machine and that a reset has been started.
Note:
The FIFO Full state forced by the reset operation is dif-
ferent from a Full state caused by normal FIFO data writes. For
normal FIFO write operations, when Full is first asserted, the
Transmit FIFO must still accept up to four additional writes of
data. When a Full state is asserted due to a Transmit FIFO
reset operation, the FIFO will not accept any additional data.
The Transmit FIFO reset does not complete until the external
reset condition is removed. This can be removed by deasser-
tion of either TXRST* or the address match. If the address
match is deasserted to remove the reset condition, the Trans-
mit FIFO flag
’
s drivers are disabled, and the Transmit FIFO
must be addressed at a later time to validate completion of the
Transmit FIFO reset. If TXRST* is deasserted (HIGH) to re-
move the reset condition, the Tx_RstMatch is changed to a
Tx_Match, and the Transmit FIFO status flags remain driven.
The Transmit FIFO reset operation is complete when the
Transmit FIFO flags indicate an Empty state (TXEMPTY* and
TXCLAV are asserted and TXFULL* is deasserted). A valid
Transmit FIFO reset sequence is shown in
Figure 11
.
Here the TXADDR[2:0] matches ADDRSEL[2:0] and TXRST*
is asserted (LOW) at the same time. When these signals are
both sampled LOW by TXCLK, a Tx_RstMatch condition is
present. With TXEN* deasserted (HIGH), the Transmit FIFO is
not selected for data transfers. This Tx_RstMatch condition
remains for eight TXCLK cycles to generate the
Tx_FIFO_Reset. Following this the TXFULL* FIFO status flag
is asserted to indicate that the Transmit FIFO reset sequence
has completed and that a Transmit FIFO reset is in progress.
When the TXRST* signal is deasserted (HIGH), TXADDR[2:0]
still matches ADDRSEL[2:0] to allow the FIFO status flags to
be driven. This allows the completion of the reset operation to
be monitored. To allow better multi-tasking on multi-PHY im-
plementations, it is possible to deassert the address match as
soon as the Full state is indicated. The FIFO reset operation
will complete and the Empty state (indicating completion of the
reset operation) can be detected during a separate polling op-
eration.
For those links implemented with a single PHY, it is possible to
hard wire TXADDR[2:0] to match ADDRSEL[2:0] and still per-
form normal accesses and reset operations. This is shown in
Figure 12
. In a single-PHY implementation with address match
always TRUE, a Transmit FIFO reset can never be initiated
with TXEN* asserted at the same time as TXRST*. Since the
address match is always TRUE, any assertion of TXEN* caus-
es the Transmit FIFO to be selected, preventing the reset
counter from advancing.
Figure 13
shows a sequence of input signals which will not
produce a FIFO reset. In this case TXEN* was asserted to
select the a Transmit FIFO for data transfers. Because TXEN*
remains active, the assertion of a TXADDR[2:0] matching
ADDRSEL[2:0] and TXRST* does not initiate a reset opera-
tion. This is shown by the TXFULL* flag remaining HIGH
(deasserted) following what would be the normal expiration of
the eight-state reset counter.
Receive FIFO Reset Sequence
The Receive FIFO reset sequence operates (for the most part)
the same as the Transmit FIFO reset sequence. The same
requirements exist for the assertion state of RXRST* and se-
lection of the interface. A sample Receive FIFO reset se-
quence is shown in
Figure 14
. Upon recognition of a Receive
FIFO reset, the Receive FIFO flags are forced to indicate an
Empty state to prohibit additional reads from the FIFO. Unlike
the Transmit FIFO, where the internal completion of the reset
operation is shown by first going Full and later going Empty
when the internal reset is complete, there is no secondary in-
dication of the completion of the internal reset of the Receive
FIFO. The Receive FIFO is usable as soon as new data is
placed into it by the Receive Control State Machine.
FIFO Reset and Continuous Selection
When configured for continuous selection (TXADDR[2:0]
matching ADDRSEL[2:0] asserted with TXEN* always en-
abled, or RXADDR[2:0] matching ADDRSEL[2:0] asserted
with RXEN* always enabled), it is not possible to reset the
Transmit and Receive FIFOs.
RXCLK
Address Match
RXEMPTY
RXRST*
Rx_RstMatch
Valid
Rx_Match
Figure 10. Receive FIFO Reset Address Match
Valid
[24]
[24]
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