參數(shù)資料
型號(hào)： CY7C954DX
廠商： Cypress Semiconductor Corp.
英文描述： ATM HOTLink Transceiver(ATM 熱接插收發(fā)器)
中文描述： 自動(dòng)柜員機(jī)的HOTLink收發(fā)器（自動(dòng)柜員機(jī)熱接插收發(fā)器）
文件頁(yè)數(shù)： 10/42頁(yè)
文件大?。?/td> 484K
代理商： CY7C954DX
CY7C954DX
PRELIMINARY
10
UTOPIA Timing Model
The UTOPIA timing model allows multiple CY7C954DX trans-
mitters to be addressed and accessed from a common host
bus, using the protocols defined in the ATM Forum UTOPIA
interface standards. It is enabled by setting EXTFIFO LOW.
In UTOPIA timing, the TXEMPTY* and TXFULL* outputs and
TXEN* input are all active LOW signals. If the CY7C954DX is
addressed by TXADDR[2:0] matching ADDRSEL[2:0], it be-
comes
“
selected
”
when TXEN* is asserted LOW. Following se-
lection, data is written into the Transmit FIFO on every clock
cycle where TXEN* remains LOW.
Cascade Timing Model
The Cascade timing model is a variation of the UTOPIA timing
model. The multi-PHY polling schemes used by UTOPIA-II do
not work in the Cascade mode. This mode is intended for
point-to-point (single PHY) use only. Here the TXEMPTY and
TXFULL* outputs, and TXEN input are all active HIGH signals.
Cascade timing makes use of the same address and selection
sequences as UTOPIA timing, but write data accesses use a
delayed write. This delayed write is necessary to allow direct
coupling to external FIFOs, or to state machines that initiate a
write operation one clock cycle before the data is available on
the bus.
Cascade timing is enabled by setting EXTFIFO HIGH.
When used for FIFO depth expansion, Cascade timing allows
the size of the internal Transmit FIFO to be expanded to an
almost unlimited depth. It allows a CY7C42x5 series synchro-
nous FIFO to be attached to the transmit interface without any
extra logic, as shown in
Figure 3
.
Transmit FIFO
The Transmit FIFO is used to buffer data captured in the input
register for later processing and transmission. This FIFO is
sized to hold 256 14-bit characters. When the Transmit FIFO
is enabled, and a Transmit FIFO write is enabled (the device
is selected and TXEN* is sampled asserted) data is captured
in the transmit input register and stored into the Transmit FIFO.
All Transmit FIFO write operations are clocked by TXCLK.
The Transmit FIFO presents Full, Half-Full, and Empty FIFO
flags. These flags are provided synchronous to TXCLK to al-
low operation with a Moore-type external controlling state ma-
chine. When configured for Cascade timing, the timing and
active levels of these signals are also designed to support di-
rect expansion to Cypress CY7C42x5 synchronous FIFOs.
The Transmit FIFO can be clocked at any rate from DC to
50 MHz. This gives the Transmit FIFO a maximum bandwidth
of 50 million characters per second. Since the serial output
speed is limited to 20 million characters per second at its fast-
est operating rate, there is ample time to service multiple
HOTLinks with a single controller.
The read port of the Transmit FIFO is connected to a logic
block that performs data formatting and validation. All data
read operations from the Transmit FIFO are controlled by a
Transmit Control State Machine that operates synchronous to
REFCLK.
Transmit Formatter and Validation
The Transmit Formatter and validation logic controls the timing
for the transfer of data from the Transmit Input Register, Trans-
mit FIFO, or Elasticity Buffer.
Transmit Data Formatting
The CY7C954DX supports a number of protocol enhance-
ments over a raw physical-layer device. These enhancements
are made possible in part through the use of the Transmit and
Receive FIFOs. These FIFOs allow the CY7C954DX to man-
age the data stream to a much greater extent than was possi-
ble before. In addition to the standard 8B/10B encoding used
to improve serial data transmission, the CY7C954DX also sup-
ports:
marking of packet or cell boundaries using TXSOC
calculation and optional insertion of Header Error Check
byte (HEC).
Both of these capabilities are supported for 8-bit encoded
characters, and use of the TXSOC bit. This bit is interpreted,
along with TXSC/D* and TXSVS to trigger HEC operations
and create three unique Start of Cell Markers. All three bits
determine how the data associated with them is processed for
transmission. These operations are listed in
Table 1
.
The entries in
Table 1
where TXSOC is LOW generate the
same characters in the serial data stream as a standard
Transmit Input Register
TXEN*
TXDATA[7:0]
8
TXCLK
REFCLK
Transmit FIFO
Figure 2. Transmit Input Register
14
TXADDR[2:0]
CONTROL
3
Address Match
ADDRSEL[2:0]
Figure 3. External FIFO Depth Expansion of the
CY7C954DX Transmit Data Path
FF*
WEN*
D
TXCLK
FF*
WEN*
D
WCLK
EF*
REN*
Q
RCLK
TXEN
TXFULL
TXDATA
TXSC/D*
TXSOC
TXSVS
TXCLK
CY7C42x5 FIFO
CY7C954DX
EXTFIFO
“
1
”
11
11
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