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參數(shù)資料
| 型號： | CY7C954DX |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | ATM HOTLink Transceiver(ATM 熱接插收發(fā)器) |
| 中文描述： | 自動柜員機的HOTLink收發(fā)器（自動柜員機熱接插收發(fā)器） |
| 文件頁數(shù)： | 5/42頁 |
| 文件大?。?/td> | 484K |
| 代理商： | CY7C954DX |
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CY7C954DX
PRELIMINARY
5
16
TXRST*
TTL input, internal
pull-up, sampled on
TXCLK
↑
,
Internal Pull-Up
TTL input,
asynchronous,
Internal Pull-Up
Transmit FIFO Reset.
When TXRST* is sampled asserted (LOW) for eight or more TXCLK cycles, a
reset operation is started on the Transmit FIFO.
7
TXBISTEN*
Transmitter BIST Enable.
When TXBISTEN* is LOW, the transmitter generates a 511-character repeat-
ing sequence, that can be used to validate link integrity. The transmitter returns
to normal operation when TXBISTEN* is HIGH. All Transmit FIFO read oper-
ations are suspended when BIST is active.
Receive Path Signals
41, 43,
45, 47,
48, 53,
59, 61
RXDATA[7:0]
3-state TTL output,
changes following
RXCLK
↑
,
Parallel Data Output.
These outputs change following the rising edge of RXCLK, when enabled to
output data (the device RXADDR[2:0] address matches ADDRSEL[2:0] and
selected by RXEN*).
Received Violation Symbol Indicator.
In Receive mode (11), this output is the indicator that data has been received
continuing errors, and is decoded in conjunction with RXSC/D* and RXSOC,
per
Table 4
, to indicate the presence of specific Special Character codes in the
received data stream.
This output is unused for the other receive modes, except that RXRVS is used
to report character mismatches when RXBISTEN* is LOW
This output changes following the rising edge of RXCLK, when enabled to
output data (the device RXADDR[2:0] address matches ADDRSEL[2:0] and
selected by RXEN*).
Receive Start Of Cell.
This output is one of the indicators for the start of a cell and is decoded in
conjunction with RXSC/D* and RXRVS, per
Table 4
, to indicate the presence
of specific Special Character codes in the received data stream.
This output changes following the rising edge of RXCLK, when enabled to
output data (the device RXADDR[2:0] address matches ADDRSEL[2:0] and
selected by RXEN*).
Received Special Character or Data Indicator.
This signal is use to differentiate between Special Characters and Data bytes.
It is also decoded in conjunction with RXSOC and RXRVS, per
Table 4
, to
indicate the presence of specific Special Character codes in the received data
stream.
This output changes following the rising edge of RXCLK, when enabled to
output data (the device RXADDR[2:0] address matches ADDRSEL[2:0] and
selected by RXEN*).
Receive Enable.
Data enable for the RXDATA bus write and read operations. Active LOW when
configured for UTOPIA timing, active HIGH when configured for Cascade tim-
ing as determined by the EXTFIFO pin.
Receive Address Input.
This is the three-bit Receive Port address that is matched to ADDRSEL[2:0] to
enable data transfer to the receiving system.
Receive Clock.
This clock is the Receive interface input clock and is used to control Receive
FIFO read, reset, and serial register access operations.
29
RXRVS
3-state TTL output,
changes following
RXCLK
↑
,
Internal Pull-Up
23
RXSOC
3-state TTL output,
changes following
RXCLK
↑
65
RXSC/D*
3-state TTL output,
changes following
RXCLK
↑
69
RXEN*
TTL input, sampled
on
RXCLK
↑
,
Internal Pull-Up
71,31,
33
RXADDR[2:0]
TTL input, sampled
on RXCLK
↑
8
RXCLK
TTL output clock,
Internal Pull-Up
Pin Descriptions
(continued)
CY7C954DX HOTLink Transceiver
Pin #
Name
I/O Characteristics
Signal Description
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